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S3C4530A product ov erview 1- 1 1 product overview introduction samsung's S3C4530A 16/32-bit risc microcontroller is a cost-effective, high-performance microcontroller solution for ethernet-based systems. an integrated ethernet controller, the S3C4530A, is designed for use in managed communication hubs and routers. the S3C4530A is built around an outstanding cpu core: the 16/32-bit arm7tdmi risc processor designed by advanced risc machines, ltd. the arm7tdmi core is a low-power, general purpose microprocessor macro-cell that was developed for use in application-specific and custom-specific integrated circuits. its simple, elegant, and fully static design is particularly suitable for cost-sensitive and power-sensitive applications. the S3C4530A offers a configurable 8-kbyte unified cache/sram and ethernet controller which reduces total system cost. most of the on-chip function blocks have been designed using an hdl synthesizer and the S3C4530A has been fully verified in samsung's state-of-the-art asic test environment. important peripheral functions include two hdlc channels with buffer descriptor, two uart channels with full modem interface signal and 32byte buffer, 2-channel gdma, two 32-bit timers, and 26 programmable i/o ports. on-board logic includes an interrupt controller, dram/ sdram controller, and a controller for rom/sram and flash memory. the system manager includes an internal 32-bit system bus arbiter and an external memory controller. the following integrated on-chip functions are described in detail in this user's manual: ? 8-kbyte unified cache/sram ? i 2 c interface ? ethernet controller ? hdlc controller ? gdma ? uart ? timers ? programmable i/o ports ? interrupt controller
product overview s3 c4530a 1- 2 features architecture integrated system for embedded ethernet applications fully 16/32-bit risc architecture little/big- endian mode supported basically, the internal architecture is big- endian. so, the little- endian mode only support for external memory. efficient and powerful arm7tdmi core cost-effective jtag-based debug solution boundary scan system manager 8/16/32-bit external bus support for rom/sram, flash memory, dram, and external i/o one external bus master with bus request/ acknowledge pins support for edo/normal or sdram programmable access cycle (0-7 wait cycles) four-word depth write buffer cost-effective memory-to-peripheral dma interface unified instruction/data cache two-way, set-associative, unified 8-kbyte cache support for lru (least recently used) protocol cache is configurable as an internal sram i 2 c serial interface master mode operation only baud rate generator for serial clock generation ethernet controller dma engine with burst mode dma tx/rx buffers (256 bytes tx, 256 bytes rx) mac tx/rx fifo buffers (80 bytes tx, 16 bytes rx) data alignment logic endian translation 100/10-mbit per second operation full compliance with ieee standard 802.3 mii(10/100mbps) or 7-wire 10-mbps interface station management signaling on-chip cam (up to 21 destination addresses ) full-duplex mode with pause feature long/short packet modes pad generation hdlcs hdlc protocol features: ? flag detection and synchronization ? zero insertion and deletion ? idle detection and transmission ? fcs generation and detection (16-bit) ? abort detection and transmission address search mode (expandable to 4 bytes) selectable crc or no crc mode automatic crc generator preset digital pll block for clock recovery baud rate generator nrz/nrzi/fm/manchester data formats for tx/rx loop-back and auto-echo modes tx/rx fifos have 8-word (8 32-bit) depth selectable 1-word or 4-word data transfer mode data alignment logic endian translation programmable interrupts modem interface up to 10 mbps operation hdlc frame length based on octets 2-channel dma buffer descriptor for tx/rx on each hdlc
S3C4530A product ov erview 1- 3 dma controller 2-channel general dma for memory-to- memory, memory-to-uart, uart-to-memory data transfers without cpu intervention initiated by a software or external dma request increments or decrements a source or destination address in 8-bit, 16-bit or 32-bit data transfers 4-data burst mode uarts two uart (serial i/o) blocks with dma-based or interrupt-based operation high speed(460kbps) uart support with 32 byte tx/rx fifo and modem interface signals support for 5-bit, 6-bit, 7-bit, or 8-bit serial data transmit and receive automatic baud rate detection eight control character comparison for software control programmable baud rates 1 or 2 stop bits odd or even parity break generation and detection parity, overrun, and framing error detection 16 clock mode infra-red (ir) tx/rx support ( irda) timers two programmable 32-bit timers interval mode or toggle mode operation programmable i/o 26 programmable i/o ports pins individually configurable to input, output, or i/o mode for dedicated signals interrupt controller 21 interrupt sources, including 4 external interrupt sources normal or fast interrupt mode (irq, fiq) prioritized interrupt handling pll the external clock can be multiplied by on-chip pll to provide high frequency system clock the input frequency range is 10-40 mhz the output frequency is 5 times of input clock. to get 50 mhz, input clock frequency should be 10 mhz. operating voltage range 3.3 v 5 % operating temperature range 0 o c to + 70 o c operating frequency up to 50 mhz package type 208 pin qfp
product overview s3 c4530a 1- 4 arm7tdmi 32-bit rise cpu cpu interface 8-kbyte unified cache 4-word write buffer bus rounter i 2 c 26 general i/o ports interruput controller uart 0,1 32-bit timer 0,1 gdma 0,1 pll memory controller with refresh control system bus arbiter 2-channel hdlcs with dmas 2-channel bdma ethernet controller bdma rams tx buffer (256 bytes) rx buffer (256 bytes) cam (128 bytes) mac tx fifo (80 bytes) rx fifo (16 bytes) tap controller for jtag mii or 7-wire remote port a,b external bus master 4-bank external i/o device 4-bank dram 6-bank rom sram flash console or modem i/f scl sda 26 i/o ports including 4: ext int req. 2: timer out (0,1) 2: ext dma req. 2: ext dma ack 14: uart figure 1-1. S3C4530A block diagram
S3C4530A product ov erview 1- 5 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 1 2 3 4 5 6 7 8 9 10 18 17 11 12 13 14 15 16 20 19 22 21 24 23 26 25 28 27 30 29 32 31 34 33 36 35 38 37 40 39 42 41 44 43 46 45 48 47 50 49 52 51 v dd v ss nuadsr1/p<23> uatxd1/p<24> nuadtr1/p<25> ndtra rxda nrtsa txda nctsa rxdb ndtrb v dd v ss ndcda rxca nsynca txca txdb nrtsb v ss v dd ndcdb nctsb nsyncb rxcb crs/crs_ 10m txcb rxd<0>/rxd_10m rx dv/link_10m v ss v dd rxd<2> rxd<1> rx err rxd<3> col/col_10m rx_clk/rxclk_10m txd<1>/loop_10m txd<0>/txd_10m v ss v dd txd<3> txd<2> txclk/txclk_10m tx_err/pocmp_10m mdio tx_en/txen_10m mdc little v ss v dd v ss v dd xdata<16> xdata<15> xdata<14> xdata<13> xdata<12> xdata<11> xdata<10> xdata<9> xdata<3> xdata<4> xdata<8> xdata<7> xdata<6> v ss v dd xdata<5> xdata<1> xdata<2> addr<21> xdata<0> addr<19> addr<20> v ss addr<18> addr<17> v dd addr<15> addr<16> addr<13> addr<14> addr<11> addr<12> addr<9> addr<10>/ap v ss addr<8> addr<7> v dd addr<5> addr<6> addr<3> addr<4> addr<1> addr<2> extmack addr<0> nwbe<3>/dqm<3> extmreq v dd v ss v dda v ssa filter v dd v ss tck tms tdi td0 ntrst tmode uclk v dd v ss necs<0> necs<1> necs<2> necs<3> newait noe bosize<0> bosize<1> nrcs<0> clkoen sdclk/mclko v dd v ss xclk v ss nreset clksel nrcs<1> nrcs<2> nrcs<3> nrcs<4> nrcs<5> nsdcs<0>/nras<0> nsdcs<1>/nras<1> nsdcs<2>/nras<2> v dd v ss nsdcs<3>/nras<3> nsdras/ncas<0> nsdcas/ncas<2> cke/ncas<2> ncas<3> ndwe dqm<0>/nwbe<0> dqm<1>/nwbe<1> dqm<2>/nwbe<2> v dd v ss 156 155 154 153 152 151 150 149 148 147 139 140 146 145 144 143 142 141 137 138 135 136 133 134 131 132 129 130 127 128 125 126 123 124 121 122 119 120 117 118 115 116 113 114 111 112 109 110 107 108 105 106 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 v ss v dd uarxd1/p<22> nuadtr0/p<21> uatxd0/p<20> nuadsr0/p<19> uarxd0/p<18> sda sca p<17>/tout1 v ss v dd p<16>/tout0 p<15>/nxdack<1> p<14>/nxdack<0> p<13>/nxdreq<1> p<12>/nxdreq<0> p<11>/xinreq<3> p<10>/xinreq<2> p<9>/xinreq<1> v ss v dd p<8>/xinreq<0> p<7>/nuarts1 p<6>/nuacts1 p<5>/nuadcd1 p<4>/nuarts0 p<3>/nuacts0 p<2>/nuadcd0 p<1> v ss v dd p<0> xdata<31> xdata<30> xdata<29> xdata<28> xdata<27> xdata<26> xdata<25> v ss v dd xdata<24> xdata<23> xdata<22> xdata<21> xdata<20> xdata<19> xdata<18> xdata<17> v ss v dd S3C4530A (208-qfp) figure 1-2. S3C4530A pin assignment diagram
product overview s3 c4530a 1- 6 signal descriptions table 1-1. S3C4530A signal descriptions signal pin no. type description xclk 80 i S3C4530A system clock source. if clksel is low, pll output clock is used as the S3C4530A internal system clock. if clksel is high, xclk is used as the S3C4530A internal system clock. mclko/sdclk (1) 77 o system clock out. mclko is monitored as the inverting phase of internal system clock, sclk. sdclk is system clock for sdram clksel 83 i clock select. when clksel is '0'(low level), pll output clock can be used as the master clock. when clksel is '1'(high level), the xclk is used as the master clock. nreset 82 i not reset. nreset is the global reset input for the S3C4530A. to allow a system reset, and for internal digital filtering, nreset must be held to low level for at least 64 master clock cycles. refer to "figure 3. S3C4530A reset timing diagram" for more details about reset timing. clkoen 76 i clock out enable/disable. (see the pin description for mclko.) tmode 63 i test mode. the tmode bit settings are interpreted as follows: '0' = normal operating mode, '1' = chip test mode. this tmode pin also can be used to change mf of pll. to get 5 times internal system clock from external clock, '0'(low level) should be assigned to tmode. if '1'(high level), mf will be changed to 6.6. filter 55 ai if the pll is used, 820pf capacitor should be connected between the pin and analog ground. tck 58 i jtag test clock. the jtag test clock shifts state information and test data into, and out of, the S3C4530A during jtag test operations. this pin is internally connected pull-down. tms 59 i jtag test mode select. this pin controls jtag test operations in the S3C4530A. this pin is internally connected pull-up. tdi 60 i jtag test data in. the tdi level is used to serially shift test data and instructions into the S3C4530A during jtag test operations. this pin is internally connected pull-up. tdo 61 o jtag test data out. the tdo level is used to serially shift test data and instructions out of the S3C4530A during jtag test operations. ntrst 62 i jtag not reset. asynchronous reset of the jtag logic. this pin is internally connected pull-up.
S3C4530A product ov erview 1- 7 table 1-1. S3C4530A signal descriptions (continued) signal pin no. type description addr[21:0]/ addr[10]/ap (1) 117-110, 129-120, 135-132 o address bus. the 22-bit address bus, addr[21:0], covers the full 4m word address range of each rom/sram, flash memory, dram, and the external i/o banks. the 23-bit internal address bus used to generate dram address. the number of column address bits in dram bank can be programmed 8bits to 11bits use by dramcon registers. addr[10]/ap is the auto pre-charge control pin. the auto pre- charge command is issued at the same time as burst read or burst write by asserting high on addr[10]/ap. xdata[31:0] 141-136, 154-144, 166-159, 175-169 i/o external (bi-directional, 32-bit) data bus. the S3C4530A data bus supports external 8-bit, 16-bit, and 32-bit bus sizes. nras[3:0]/ nsdcs[3:0] (1) 94, 91, 90, 89 o not row address strobe for dram. the S3C4530A supports up to four dram banks. one nras output is provided for each bank. nsdcs[3:0] are chip select pins for sdram. ncas[3:0] ncas[0]/ nsdras ncas[1]/ nsdcas ncas[2]/cke (1) 98, 97, 96, 95 o not column address strobe for dram. the four ncas outputs indicate the byte selections whenever a dram bank is accessed. nsdras is row address strobe signal for sdram. latches row addresses on the positive going edge of the sdclk with nsdras low. enable row access and pre-charge. nsdcas is column address strobe for sdram. latches column addresses on the positive going edge of the sdclk with nsdcas low. enables column access. cke is clock enable signal for sdram. masks sdram system clock, sdclk to freeze operation from the next clock cycle. sdclk should be enabled at least one cycle prior to new command. disable input buffers of sdram for power down in standby. ndwe 99 o dram not write enable. this pin is provided for dram bank write operations. ( nwbe[3:0] is used for write operations to the rom/ sram/flash memory banks.) . necs[3:0] 70, 69, 68, 67 o not external i/o chip select. four external i/o banks are provided for external memory-mapped i/o operations. each i/o bank stores up to 16 kbytes. necs signals indicate which of the four external i/o banks is selected. newait 71 i not external wait. this signal is activated when an external i/o device or rom/sram/flash bank 0 to 5 needs more access cycles than those defined in the corresponding control register.
product overview s3 c4530a 1- 8 table 1-1. S3C4530A signal descriptions (continued) signal pin no. type description nrcs[5:0] 88, 84, 75 o not rom/sram/flash chip select. the S3C4530A can access up to six external rom/sram/flash banks. by controlling the nrcs signals, you can map cpu addresses into the physical memory banks. b0size[1:0] 74, 73 i bank 0 data bus access size. bank 0 is used for the boot program. you use these pins to set the size of the bank 0 data bus as follows: '01' = one byte, '10' = half-word, '11' = one word, and '00' = reserved. noe 72 o not output enable. whenever a memory access occurs, the noe output controls the output enable port of the specific memory device. nwbe[3:0]/ dqm[3:0] (1) 107, 102, 100 o not write byte enable. whenever a memory write access occurs, the nwbe output controls the write enable port of the specific memory device (except for dram). for dram banks, cas[3:0] and ndwe are used for the write operation. dqm is data input/output mask signal for sdram. extmreq 108 i external bus master request. an external bus master uses this pin to request the external bus. when it activates the extmreq signal, the S3C4530A drives the state of external bus pins to high impedance. this lets the external bus master take control of the external bus. when it has the control, the external bus master assumes responsibility for dram refresh operations. the extmreq signal is deactivated when the external bus master releases the external bus. when this occurs, extmack goes low level and the S3C4530A assumes the control of the bus. extmack 109 o external bus acknowledge. (see the extmreq pin description.) mdc 50 o management data clock. the signal level at the mdc pin is used as a timing reference for data transfers that are controlled by the mdio signal. mdio 48 i/o management data i/o. when a read command is being executed, data that is clocked out of the phy is presented on this pin. when a write command is being executed, data that is clocked out of the controller is presented on this pin for the physical layer entity, phy. little 49 i little endian mode selection pin. if little is high, S3C4530A operate in little endian mode. if low, then in big endian mode. default value is low because this pin is pull-downed internally. col/col_10m 38 i collision detected/collision detected for 10m. col is asserted asynchronously with minimum delay from the start of a collision on the medium in mii mode. col_10m is asserted when a 10- mbit/s phy detects a collision.
S3C4530A product ov erview 1- 9 table 1-1. S3C4530A signal descriptions (continued) signal pin no. type description tx_clk/ txclk_10m 46 i transmit clock/transmit clock for 10m. the controller drives txd[3:0] and tx_en from the rising edge of tx_clk. in mii mode, the phy samples txd[3:0] and tx_en on the rising edge of tx_clk. for data transfers, txclk_10m is provided by the 10-mbit/s phy. txd[3:0] loop_10m txd_10m 44, 43, 40, 39 o transmit data/transmit data for 10m/loop-back for 10m. transmit data is aligned on nibble boundaries. txd[0] corresponds to the first bit to be transmitted on the physical medium, which is the lsb of the first byte and the fifth bit of that byte during the next clock. txd_10m is shared with txd[0] and is a data line for transmitting to the 10-mbit/s phy. loop_10m is shared with txd[1] and is driven by the loop-back bit in the control register. tx_en/ txen_10m 47 o transmit enable/transmit enable for 10m. tx_en provides precise framing for the data carried on txd[3:0]. this pin is active during the clock periods in which txd[3:0] contains valid data to be transmitted from the preamble stage through crc. when the controller is ready to transfer data, it asserts txen_10m. tx_err/ pcomp_10m 45 o transmit error/packet compression enable for 10m. tx_err is driven synchronously to tx_clk and sampled continuously by the physical layer entity, phy. if asserted for one or more tx_clk periods, tx_err causes the phy to emit one or more symbols which are not part of the valid data, or delimiter set located somewhere in the frame that is being transmitted. pcomp_10m is asserted immediately after the packet ? s da field is received. pcomp_10m is used with the management bus of the dp83950 repeater interface controller (from national semiconductor). the mac can be programmed to assert pcomp if there is a cam match, or if there is not a match. the ric (repeater interface controller) uses this signal to compress (shorten) the packet received for management purposes and to reduce memory usage. (see the dp83950 data sheet, published by national semiconductor, for details on the ric management bus.) this pin is controlled by a special register, with which you can define the polarity and assertion method (cam match active or not match active) of the pcomp signal. crs/crs_10m 28 i carrier sense/carrier sense for 10m. crs is asserted asynchronously with minimum delay from the detection of a non- idle medium in mii mode. crs_10m is asserted when a 10- mbit/s phy has data to transfer. a 10-mbit/s transmission also uses this signal. rx_clk/ rxclk_10m 37 i receive clock/receive clock for 10m. rx_clk is a continuous clock signal. its frequency is 25 mhz for 100-mbit/s operation, and 2.5 mhz for 10-mbit/s. rxd[3:0], rx_dv, and rx_err are driven by the phy off the falling edge of rx_clk, and sampled on the rising edge of rx_clk. to receive data, the rxclk_10 m clock comes from the 10mbit/s phy.
product overview s3 c4530a 1- 10 table 1-1. S3C4530A signal descriptions (continued) signal pin no. type description rxd[3:0]/ rxd_10m 35, 34, 33, 30 i receive data/receive data for 10m. rxd is aligned on nibble boundaries. rxd[0] corresponds to the first bit received on the physical medium, which is the lsb of the byte in one clock period and the fifth bit of that byte in the next clock. rxd_10m is shared with rxd[0] and it is a line for receiving data from the 10- mbit/s phy. rx_dv/link_10m 29 i receive data valid/link status for 10m. phy asserts rx_dv synchronously, holding it active during the clock periods in which rxd[3:0] contains valid data received. phy asserts rx_dv no later than the clock period when it places the first nibble of the start frame delimiter (sfd) on rxd[3:0]. if phy asserts rx_dv prior to the first nibble of the sfd, then rxd[3:0] carries valid preamble symbols. link_10m is shared with rx_dv and used to convey the link status of the 10-mbit/s endec. the value is stored in a status register. rx_err 36 i receive error. phy asserts rx_err synchronously whenever it detects a physical medium error (e.g., a coding violation). phy asserts rx_err only when it asserts rx_dv. txda 9 o hdlc ch-a transmit data. the serial output data from the transmitter is coded in nrz/nrzi/fm/manchester data format. rxda 7 i hdlc ch-a receive data. the serial input data received by the device should be coded in nrz/nrzi/fm/manchester data format. the data rate should not exceed the rate of the S3C4530A internal master clock. ndtra 6 o hdlc ch-a data terminal ready. ndtra output indicates that the data terminal device is ready for transmission and reception. nrtsa 8 o the nrts pin goes low at that time the data into the txfifo. and this pin output state can be controlled directly using rts bit in tcon register. if this bit set to one, nrts goes low state. if the autoen bit set to one, the data in txfifo can be transmitted only when the ncts state has low. if autoen bit set to zero, the data in txfifo can be transmitted irrespective of the ncts state. nctsa 10 i hdlc ch-a clear to send. the S3C4530A stores each transition of ncts to ensure that its occurrence would be acknowledged by the system. if autoen bit set to one, it is possible to transmit data only when ncts active state. ndcda 13 i hdlc ch-a data carrier detected. if autoen bit is set to one, high level on this pin resets and inhibits the receiver register. data from a previous frame that may remain in the rxfifo is retained. the S3C4530A stores each transition of ndcd. if autoen bit set to one, it is possible to receive data only when ndcd active state. nsynca 15 o hdlc ch-a sync is detected. this indicates the reception of a flag. the nsync output goes low for one bit time beginning at the last bit of the flag.
S3C4530A product ov erview 1- 11 table 1-1. S3C4530A signal descriptions (continued) signal pin no. type description rxca 14 i hdlc ch-a receiver clock. when this clock input is used as the receiver clock, the receiver samples the data on the positive edge of rxca clock. it is possible to samples the data on the negative edge by register setting. this clock can be the source clock of the receiver, the baud rate generator, or the dpll. txca 16 i/o hdlc ch-a transmitter clock. when this clock input is used as the transmitter clock, the transmitter shifts data on the negative transition of the txca clock . it is possible to samples the data on the positive edge by register setting. if you do not use txca as the transmitter clock, you can use it as an output pin for monitoring internal clocks such as the transmitter clock, receiver clock, and baud rate generator output clocks. txdb 20 o hdlc ch-b transmit data. see the txda pin description. rxdb 18 i hdlc ch-b receive data. see the rxda pin description. ndtrb 17 o hdlc ch-b data terminal ready. see the ndtra pin description. nrtsb 19 o hdlc ch-b request to send. see the nrtsa pin description. nctsb 23 i hdlc ch-b clear to send. see the nctsa pin description. ndcdb 24 i hdlc ch-b data carrier detected. see the ndcda pin description. nsyncb 26 o hdlc ch-b sync is detected. see the nsynca pin description. rxcb 25 i hdlc ch-b receiver clock. see the rxca pin description. txcb 27 i/o hdlc ch-b transmitter clock. see the txca pin description. uclk 64 i the external uart clock input. mclk or pll generated clock can be used as the uart clock. you can use uclk, with an appropriate divided by factor, if a very precious baud rate clock is required. uarxd0/p[18] 202 i/b uart0 receive data. rxd0 is the uart0 input signal for receiving serial data. this pin can be used general i/o port also. it can be controlled by iopcon register. see chapter 12. uatxd0/p[20] 204 o/b uart0 transmit data. txd0 is the uart0 output signal for transmitting serial data. this pin can be used general i/o port also. it can be controlled by iopcon register. see chapter 12. nuadsr0/p[19] 203 i/b not uart0 data set ready. this input signals in the uart0 that the peripheral (or host) is ready to transmit or receive serial data. see chapter 10. nuadtr0/p[21] 205 o/b not uart0 data terminal ready. this output signals the host (or peripheral) that uart0 is ready to transmit or receive serial data. this pin output state can be controlled by uart0 control register.
product overview s3 c4530a 1- 12 table 1-1. S3C4530A signal descriptions (continued) signal pin no. type description nuadcd0/p[2] 180 i/b this input pin function is determined by hardware flow control bit value in uart control register. if hardware flow control bit set to one, uart can receive the receiving data only when this pin state is active. nuacts0/p[3] 181 i/b this input pin function controlled by hardware flow control bit value in uart control register. if hardware flow control bit set to one, uart can transmit the transmitting data only when this pin state is active. nuarts0/p[4] 182 o/b this pin output state goes low or high according to the transmit data is in tx buffer or tx fifo when hardware flow control bit value set to one in uart control register. if tx buffer or tx fifo has data to send, this pin state goes low. if hardware flow control bit is zero, this pin output can be controlled directly by uart control register[25] bit value. uarxd1/p[22] 206 i/b see uart0 description. uatxd1/p[24] 4 o/b see uart0 description. nuadtr1/p[25] 5 o/b see uart0 description. nuadsr1/p[23] 3 i/b see uart0 description. nuadcd1/p[5] 183 i/b see uart0 description. nuacts1/p[6] 184 i/b see uart0 description. nuarts1/p[7] 185 o/b see uart0 description.
S3C4530A product ov erview 1- 13 table 1-1. S3C4530A signal descriptions (continued) signal pin no. type description p[1:0] 179, 176 i/o general i/o ports. see the i/o ports, chapter 12. xintreq[3:0] p[11:8] 191 - 189, 186 i/o external interrupt request lines or general i/o ports. see the i/o ports, chapter 12. nxdreq[1:0]/ p[13:12] 193, 192 i/o not external dma requests for gdma or general i/o ports. see the i/o ports, chapter 12. nxdack[1:0] p[15:14] 195, 194 i/o not external dma acknowledge from gdma or general i/o ports. see the i/o ports, chapter 12. tout0/p[16] 196 i/o timer 0 out or general i/o port. see the i/o ports, chapter 12. tout1/p[17] 199 i/o timer 1 out or general i/o port. see the i/o ports, chapter 12. scl 200 i/o i2c serial clock. sda 201 i/o i2c serial data. vddp 1, 21, 41, 56, 78, 92, 105, 118, 130, 155, 167, 177, 197 power i/o pad power vddi 11, 31, 51, 65, 103, 142, 157, 187, 207 power internal core power vssp 2, 22, 42, 57, 79, 81, 93, 106, 119, 131, 156, 168, 178, 198 gnd i/o pad ground vssi 12, 32, 52, 66, 104, 143, 158, 188, 208 gnd internal core ground vdda 53 power analog power for pll vssa/vbba 54 gnd analog/bulk ground for pll note: sdram or edo/normal dram interface signal pins are shared functions. it s functions will be configured by syscfg[31].
product overview s3 c4530a 1- 14 table 1-2. S3C4530A pin list and pad type group pin name pin counts i/o type pad type description system xclk 1 i ptic S3C4530A system source clock. configuration mclko 1 o pob4 system clock out. (8) clksel 1 i ptic clock select. nreset 1 i ptis not reset. clkoen 1 i ptic clock out enable/disable. tmode 1 i ptic test mode. little 1 i pticd little endian mode select pin filter 1 i pia_bb pll filter pin tap control tck 1 i ptic jtag test clock. (5) tms 1 i pticu jtag test mode select. tdi 1 i pticu jtag test data in. tdo 1 o ptot2 jtag test data out. ntrst 1 i pticu jtag not reset. memory addr[21:0] 22 o ptot6 address bus. interface xdata[31:0] 32 i/o ptbsut6 external, bi-directional, 32-bit data bus. (83) nras[3:0] 4 o ptot4 not row address strobe for dram. ncas[3:0] 4 o ptot4 not column address strobe for dram. ndwe 1 o ptot4 not write enable for dram. necs[3:0] 4 o ptot4 not external i/o chip select. newait 1 i ptic not external wait signal. nrcs[5:0] 6 o ptot4 not rom/sram/flash chip select. b0size[1:0] 2 i ptic bank 0 data bus access size. noe 1 o ptot4 not output enable. nwbe[3:0] 4 o ptot4 not write byte enable. extmreq 1 i ptic external master bus request. extmack 1 o pob1 external bus acknowledge.
S3C4530A product ov erview 1- 15 table 1-2. S3C4530A pin list and pad type (continued) group pin name pin counts i/o type pad type description ethernet mdc 1 o pob4 management data clock. controller mdio 1 i/o ptbcut4 management data i/o. (18) col/ col_10m 1 i ptis collision detected/collision detected for 10m. tx_clk/ txclk_10m 1 i ptis transmit data/transmit data for 10m. txd[3:0]/txd_10m 4 o pob4 transmit data/transmit data for 10m. tx_en/ txen_10m 1 o pob4 transmit enable or transmit enable for 10m. tx_err/ pcomp_10m 1 o pob4 transmit error/packet compression enable for 10m. crs/ crs_10m 1 i ptis carrier sense/carrier sense for 10m. rx_clk/ rxclk_10m 1 i ptis receive clock/receive clock for 10m. rxd[3:0]/ rxd_10m 4 i ptis receive data/receive data for 10m. rx_dv/ link_10m 1 i ptis receive data valid. rx_err 1 i ptis receive error. hdlc txda 1 o pob4 hdlc channel a transmit data. channel a rxda 1 i ptis hdlc channel a receive data. (9) ndtra 1 o pob4 hdlc channel a data terminal ready. nrtsa 1 o pob4 hdlc channel a request to send. nctsa 1 i ptis hdlc channel a clear to send. ndcda 1 i ptis hdlc channel a data carrier detected. nsynca 1 o pob4 hdlc channel a sync is detected. rxca 1 i ptis hdlc channel a receiver clock. txca 1 i/o ptbsut1 hdlc channel a transmitter clock. hdlc txdb 1 o pob4 hdlc channel b transmit data. channel b rxdb 1 i ptis hdlc channel b receive data. (9) ndtrb 1 o pob4 hdlc channel b data terminal ready. nrtsb 1 o pob4 hdlc channel b request to send. nctsb 1 i ptis hdlc channel b clear to send. ndcdb 1 i ptis hdlc channel b data carrier detected. nsyncb 1 o pob4 hdlc channel b sync is detected. rxcb 1 i ptis hdlc channel b receiver clock. txcb 1 i/o ptbsut1 hdlc channel b transmitter clock.
product overview s3 c4530a 1- 16 table 1-2. S3C4530A pin list and pad type (continued) group pin name pin counts i/o type pad type description uart 0 (8) uclk 1 i ptis uart external clock for uart0/uart1 uarxd0/ p[18] 1 i/b ptbst4sm uart 0 receive data. uatxd0/ p[20] 1 o/b ptbst4sm uart 0 transmit data. nuadtr0/ p[21] 1 o/b ptbst4sm not uart 0 data terminal ready. nuadsr0/ p[19] 1 i/b ptbst4sm not uart0 data set ready. nuadcd0/ p[2] 1 i/b ptbst4sm not uart0 data carrier detect. nuacts0/ p[3] 1 i/b ptbst4sm not uart0 clear to send. nuarts0/ p[4] 1 o/b ptbst4sm not uart0 request to send uart 1 (7) uarxd1/ p[22] 1 i/b ptbst4sm uart 1 receive data. uatxd1/ p[24] 1 o/b ptbst4sm uart 1 transmit data. nuadtr1/ p[25] 1 o/b ptbst4sm not uart 1 data terminal ready. nuadsr1/ p[23] 1 i/b ptbst4sm not uart 1 data set ready. nuadcd1/ p[5] 1 i/b ptbst4sm not uart1 data carrier detect. nuacts1/ p[6] 1 i/b ptbst4sm not uart1 clear to send. nuarts1/ p[7] 1 o/b ptbst4sm not uart1 request to send general p[1:0] 2 i/o ptbst4sm general i/o port. purpose i/o port xintreq [3:0] /p[11:8] 4 i/o ptbst4sm external interrupt request or general i/o port. (xintreq, nxdreq, nxdreq[1:0] / p[13:12] 2 i/o ptbst4sm external dma requests for gdma or general i/o ports. nxdack, timer0,1), nxdack[1:0] / p[15:14] 2 i/o ptbst4sm external dma acknowledge from gdma or general i/o ports. (18) timer0/ p[16] 1 i/o ptbst4sm timer 0 out or general i/o port. timer1/ p[17] 1 i/o ptbst4sm timer 1 out or general i/o port. i 2 c (2) scl 1 i/o ptbcd4 i2c serial clock. sda 1 i/o ptbcd4 i2c serial data.
S3C4530A product ov erview 1- 17 table 1-3. S3C4530A pad type pad type i/o type current drive cell type feature slew-rate control ptic i - lvcmos level 5v-tolerant - ptis i - lvcmos schmit trigger level 5v-tolerant - pticu i - lvcmos level 5v-tolerant pull-up register - pticd i - lvcmos level 5v-tolerant pull-down register - pia_bb i - analog input with separate bulk bias - - pob1 o 1ma normal buffer - - ptot2 o 2ma tri-state buffer 5v-tolerant - pob4 o 4ma normal buffer - - ptot4 o 4ma tri-state buffer 5v-tolerant - ptot6 o 6ma tri-state buffer 5v-tolerant - ptbsut1 i/o 1ma lvcmos schmit trigger level tri- state buffer 5v-tolerant pull-up register - ptbcut4 i/o 4ma lvcmos level tri-state buffer 5v-tolerant medium ptbcd4 i/o 4ma lvcmos level open drain buffer 5v-tolerant - ptbst4sm i/o 4ma lvcmos schmit trigger level 5v-tolerant medium ptbsut6 i/o 6ma lvcmos schmit trigger level 5v-tolerant pull-up register - note: pticu and pticd provides 100k ohm pull-up(down) register. for detail information about the pad type, see chapter 4. input/output cells of the "std90/mdl90 0.35um 3.3v standard cell library data book", produced by samsung electronics co., ltd, asic team 64*f mclk 512*f mclk nreset nrsco note : after the falling edge of nreset, the S3C4530A count 64 cycles for a system reset and ne eds further 512 cycles for a tag ram clear of cache. after the se cycles , the S3C4530A asserts nrcs0 when the nreset is released. figure 1-3. reset timing diagram
product overview s3 c4530a 1- 18 cpu core overview the S3C4530A cpu core is a general purpose 32-bit arm7tdmi microprocessor, developed by advanced risc machines, ltd. (arm). the core architecture is based on reduced instruction set computer (risc) principles. the risc architecture makes the instruction set and its related decoding mechanism simpler and more efficient than those with microprogrammed complex instruction set computer (cisc) systems. high instruction throughput and impressive real-time interrupt response are among the major benefits of the architecture. pipelining is also employed so that all components of the processing and memory systems can operate continuously. the arm7tdmi has a 32 -bit address bus. an important feature of the arm7tdmi processor that makes itself distinct from the arm7 processor is a unique architectural strategy called thumb . the thumb strategy is an extension of the basic arm architecture consisting of 36 instruction formats. these formats are based on the standard 32-bit arm instruction set, while having been re-coded using 16-bit wide opcodes. as thumb instructions are one-half the bit width of normal arm instructions, they produce very high-density codes. when a thumb instruction is executed, its 16-bit opcode is decoded by the processor into its equivalent instruction in the standard arm instruction set. the arm core then processes the 16-bit instruction as it would a normal 32-bit instruction. in other words, the thumb architecture gives 16-bit systems a way to access the 32-bit performance of the arm core without requiring the full overhead of 32-bit processing. as the arm7tdmi core can execute both standard 32-bit arm instructions and 16-bit thumb instructions, it allows you to mix the routines of thumb instructions and arm code in the same address space. in this way, you can adjust code size and performance, routine by routine, to find the best programming solution for a specific application. address register address incrementer register bank multiplier barrel shifter 32-bit alu write data register instruction decoder and logic controll instruction pipeline and read data register figure 1-4. arm7tdmi core block diagram
S3C4530A product ov erview 1- 19 instruction set the S3C4530A instruction set is divided into two subsets: a standard 32-bit arm instruction set and a 16-bit thumb instruction set . the 32-bit arm instruction set is comprised of thirteen basic instruction types, which can, in turn, be divided into four broad classes: four types of branch instructions which control program execution flow, instruction privilege leve ls, and switching between an arm code and a thumb code. three types of data processing instructions which use the on-chip alu, barrel shifter, and multiplier to perform high-speed data operations in a bank of 31 registers (all with 32-bit register widths). three types of load and store instructions which control data transfer between memory locations and the registers. one type is optimized for flexible addressing, another for rapid context switching, and the third for swapping data. three types of co-processor instructions which are dedicated to controlling external co-processors. these instructions extend the off-chip functionality of the instruction set in an open and uniform way. note all 32-bit arm instructions can be executed conditionally. the 16-bit thumb instruction set contains 36 instruction formats drawn from the standard 32-bit arm instruction set. the thumb instructions can be divided into four functional groups: four branch instructions. twelve data processing instructions, which are a subset of the standard arm data processing instructions. eight load and store register instructions. four load and store multiple instructions. note each 16-bit thumb instruction has a corresponding 32-bit arm instruction with an identical processing model. the 32-bit arm instruction set and the 16-bit thumb instruction set are good targets for compilers of many different high -level languages. when an assembly code is required for critical code segments, the arm programming technique is straightforward, unlike that of some risc processors which depend on sophisticated compiler technology to manage complicated instruction interdependencies. pipelining is employed so that all parts of the processor and memory systems can operate continuously. typically, while one instruction is being executed, its successor is being decoded, and the third instruction is being fetched from memory.
product overview s3 c4530a 1- 20 memory interface the cpu memory interface has been designed to help the highest performance potential to be realized without incurring high costs in the memory system. speed-critical control signals are pipelined so that system control functions can be implemented in standard low-power logic. these pipelined control signals allow you to fully exploit the fast local access modes, offered by industry standard dynamic rams. operating states from a programmer s point of view, the arm7tdmi core is always in one of two operating states. these states, which can be switched by software or by exception processing, are: arm state (when executing 32-bit, word-aligned, arm instructions), and thumb state (when executing 16-bit, half-word aligned thumb instructions). operating modes the arm7tdmi core supports seven operating modes: user mode : a normal program execution state fiq (fast interrupt request) mode : for supporting a specific data transfer or channel processing irq (interrupt request) mode : for general purpose interrupt handling supervisor mode : a protected mode for the operating system abort mode : entered when a data or instruction pre-fetch is aborted system mode : a privileged user mode for the operating system undefined mode : entered when an undefined instruction is executed operating mode changes can be controlled by software. they can also be caused by external interrupts or exception processing. most application programs execute in user mode. privileged modes (that is, all modes other than user mode) are entered to service interrupts or exceptions, or to access protected resources.
S3C4530A product ov erview 1- 21 registers the S3C4530A cpu core has a total of 37 registers: 31 general-purpose 32-bit registers, and 6 status registers. not all of these registers are always available. whether a registers is available to the programmer at any given time depends on the current processor operating state and mode. note when the S3C4530A is operating in arm state, 16 general registers and one or two status registers can be accessed at any time. in privileged mode, mode-specific banked registers are switched in. two register sets, or banks, can also be accessed, depending on the core s current state, the arm state register set and the thumb state register set : the arm state register set contains 16 directly accessible registers: r0-r15. all of these registers, except for r15, are for general-purpose use, and can hold either data or address values. an additional (17th) register, the cpsr (current program status register), is used to store status information. the thumb state register set is a subset of the arm state set. you can access 8 general registers, r0-r7, as well as the program counter (pc), a stack pointer register (sp), a link register (lr), and the cpsr. each privileged mode has a corresponding banked stack pointer, link register, and saved process status register (spsr). the thumb state registers are related to the arm state registers as follows: thumb state r0-r7 registers and arm state r0-r7 re gisters are identical thumb state cpsr and spsrs and arm state cpsr and spsrs are identical thumb state sp, lr, and pc are mapped directly to arm state registers r13, r14, and r15, respectively in thumb state, registers r8-r15 are not part of the standard register set. however, you can access them for assembly language programming and use them for fast temporary storage, if necessary.
product overview s3 c4530a 1- 22 exceptions an exception arises when the normal flow of program execution is interrupted, e.g., when processing is diverted to handle an interrupt from a peripheral. the processor state just prior to handling the exception must be preserved so that the program flow can be resumed when the exception routine is completed. multiple exceptions may arise simultaneously. to process exceptions, the S3C4530A uses the banked core registers to save the current state. the old pc value and the cpsr contents are copied into the appropriate r14 (lr) and spsr registers the pc and mode bits in the cpsr are adjusted to the value corresponding to the type of exception being processed. the S3C4530A core supports seven types of exceptions. each exception has a fixed priority and a corresponding privileged processor mode, as shown in table 1-4. table 1-4. S3C4530A cpu exceptions exception mode on entry priority reset supervisor mode 1 (highest) data abort abort mode 2 fiq fiq mode 3 irq irq mode 4 prefetch abort abort mode 5 undefined instruction undefined mode 6 swi supervisor mode 6 (lowest)
S3C4530A product ov erview 1- 23 special registers table 1-5. S3C4530A special registers group registers offset r/w description reset/value system syscfg 0x0000 r/w system configuration register 0x4fffff91 manager clkcon 0x3000 r/w clock control register 0x00000000 extacon0 0x3008 r/w external i/o timing register 1 0x00000000 extacon1 0x300c r/w external i/o timing register 2 0x00000000 extdbwth 0x3010 r/w data bus width for each memory bank 0x00000000 romcon0 0x3014 r/w rom/sram/flash bank 0 control register 0x20000060 romcon1 0x3018 r/w rom/sram/flash bank 1 control register 0x00000060 romcon2 0x301c r/w rom/sram/flash bank 2 control register 0x00000060 romcon3 0x3020 r/w rom/sram/flash bank 3 control register 0x00000060 romcon4 0x3024 r/w rom/sram/flash bank 4 control register 0x00000060 romcon5 0x3028 r/w rom/sram/flash bank 5 control register 0x00000060 dramcon0 0x302c r/w dram bank 0 control register 0x00000000 dramcon1 0x3030 r/w dram bank 1 control register 0x00000000 dramcon2 0x3034 r/w dram bank 2 control register 0x00000000 dramcon3 0x3038 r/w dram bank 3 control register 0x00000000 refextcon 0x303c r/w refresh and external i/o control register 0x000083ed ethernet bdmatxcon 0x9000 r/w buffered dma receive control register 0x00000000 (bdma) bdmarxcon 0x9004 r/w buffered dma transmit control register 0x00000000 bdmatxptr 0x9008 r/w transmit frame descriptor start address 0x00000000 bdmarxptr 0x900c r/w receive frame descriptor start address 0x00000000 bdmarxlsz 0x9010 r/w receive frame maximum size undefined bdmastat 0x9014 r/w buffered dma status 0x00000000 cam 0x9100- 0x917c w cam content (32 words) undefined bdmatxbuf 0x9200- 0x92fc r/w bdma tx buffer (64 words) for test mode addressing undefined bdmarxbuf 0x9800- 0x99fc r/w bdma rx buffer (64 words) for test mode addressing undefined ethernet macon 0xa000 r/w ethernet mac control register 0x00000000 (mac) camcon 0xa004 r/w cam control register 0x00000000 mactxcon 0xa008 r/w mac transmit control register 0x00000000 mactxstat 0xa00c r/w mac transmit status register 0x00000000 macrxcon 0xa010 r/w mac receive control register 0x00000000 macrxstat 0xa014 r/w mac receive status register 0x00000000
product overview s3 c4530a 1- 24 table 1-5. S3C4530A special registers (continued) group registers offset r/w description reset/value ethernet stadata 0xa018 r/w station management data 0x00000000 (mac) stacon 0xa01c r/w station management control and address 0x00006000 camen 0xa028 r/w cam enable register 0x00000000 emisscnt 0xa03c r/w missed error count register 0x00000000 epzcnt 0xa040 r pause count register 0x00000000 ermpzcnt 0xa044 r remote pause count register 0x00000000 etxstat 0x9040 r transmit control frame status 0x00000000 hdlc hmode 0x7000 r/w hdlc mode register 0x00000000 channel a hcon 0x7004 r/w hdlc control register 0x00000000 hstat 0x7008 r/w hdlc status register 0x00010400 hinten 0x700c r/w hdlc interrupt enable register 0x00000000 htxfifoc 0x7010 w txfifo frame continue register - htxfifot 0x7014 w txfifo frame terminate register - hrxfifo 0x7018 r hdlc rxfifo entry register 0x00000000 hbrgtc 0x701c r/w hdlc baud rate generate time constant 0x00000000 hprmb 0x7020 r/w hdlc preamble constant 0x00000000 hsar0 0x7024 r/w hdlc station address 0 0x00000000 hsar1 0x7028 r/w hdlc station address 1 0x00000000 hsar2 0x702c r/w hdlc station address 2 0x00000000 hsar3 0x7030 r/w hdlc station address 3 0x00000000 hmask 0x7034 r/w hdlc mask register 0x00000000 hdmatxptr 0x7038 r/w dma tx buffer descriptor pointer 0x00000000 hdmarxptr 0x703c r/w dma rx buffer descriptor pointer 0x00000000 hmflr 0x7040 r/w maximum frame length register 0x00000000 hrbsr 0x7040 r/w dma receive buffer size register 0x00000000 hsync 0x7048 r/w hdlc sync register 0x7e tcon 0x704c r/w transparent control register 0x00000000 hdlc hmode 0x8000 r/w hdlc mode register 0x00000000 channel b hcon 0x8004 r/w hdlc control register 0x00000000 hstat 0x8008 r/w hdlc status register 0x00010400 hinten 0x800c r/w hdlc interrupt enable register 0x00000000 htxfifoc 0x8010 w txfifo frame continue register 0x00000000 htxfifot 0x8014 w txfifo frame terminate register 0x00000000 hrxfifo 0x8018 r hdlc rxfifo entry register 0x00000000 hbrgtc 0x801c r/w hdlc baud rate generate time constant 0x00000000 hprmb 0x8020 r/w hdlc preamble constant 0x00000000
S3C4530A product ov erview 1- 25 table 1-5. S3C4530A special registers (continued) group registers offset r/w description reset/value hdlc hsar0 0x8024 r/w hdlc station address 0 0x00006000 channel b hsar1 0x8028 r/w hdlc station address 1 0x00000000 hsar2 0x802c r/w hdlc station address 2 0x00000000 hsar3 0x8030 r hdlc station address 3 0x00000000 hmask 0x8034 r hdlc mask register 0x00000000 hdmatxptr 0x8038 r dma tx buffer descriptor pointer 0x00000000 hdmarxptr 0x803c r/w dma rx buffer descriptor pointer 0x00000000 hmflr 0x8040 r/w maximum frame length register 0x00000000 hrbsr 0x8044 r/w dma receive buffer size register 0x00000000 hsync 0x8048 r/w hdlc sync register 0x7e tcon 0x804c r/w transparent control register 0x00000000 i/o ports iopmod 0x5000 r/w i/o port mode register 0x00000000 iopcon 0x5004 r/w i/o port control register 0x00000000 iopdata 0x5008 r/w input port data register 0x00000000 interrupt intmod 0x4000 r/w interrupt mode register undefined controller intpnd 0x4004 r/w interrupt pending register 0x00000000 intmsk 0x4008 r/w interrupt mask register 0x00000000 intpri0 0x400c r/w interrupt priority register 0 0x003fffff intpri1 0x4010 r/w interrupt priority register 1 0x07060504 intpri2 0x4014 r/w interrupt priority register 2 0x0b0a0908 intpri3 0x4018 r/w interrupt priority register 3 0x0f0e0d0c intpri4 0x401c r/w interrupt priority register 4 0x13121110 intpri5 0x4020 r/w interrupt priority register 5 0x00000014 intoffset 0x4024 r interrupt offset address register 0x00000054 intoset_fiq 0x4030 r fiq interrupt offset register 0x00000054 intoset_irq 0x4034 r irq interrupt offset register 0x00000054 i 2 c bus iiccon 0xf000 r/w i 2 c bus control status register 0x00000054 iicbuf 0xf004 r/w i 2 c bus shift buffer register undefined iicps 0xf008 r/w i 2 c bus prescaler register 0x00000000 iiccount 0xf00c r i 2 c bus prescaler counter register 0x00000000 gdma gdmacon0 0xb000 r/w gdma channel 0 control register 0x00000000 gdmacon1 0xc000 r/w gdma channel 1 control register 0x00000000 gdmasrc0 0xb004 r/w gdma source address register 0 undefined gdmadst0 0xb008 r/w gdma destination address register 0 undefined
product overview s3 c4530a 1- 26 table 1-5. S3C4530Ac special registers (continued) group registers offset r/w description reset/value gdma gdmasrc1 0xc004 r/w gdma source address register 1 undefined gdmadst1 0xc008 r/w gdma destination address register 1 undefined gdmacnt0 0xb00c r/w gdma channel 0 transfer count register undefined gdmacnt1 0xc00c r/w gdma channel 1 transfer count register undefined uart ucon0 0xd000 r/w uart channel 0 control register 0x00 ucon1 0xe000 r/w uart channel 1 control register 0x00 ustat0 0xd004 r/w uart channel 0 status register 0xe0240 ustat1 0xe004 r/w uart channel 1 status register 0xe0240 uinten0 0xd008 r/w uart channel 0 interrupt enable register 0x00000000 uinten1 0xe008 r/w uart channel 1 interrupt enable register 0x00000000 utxbuf0 0xd00c w uart channel 0 transmit holding register undefined utxbuf1 0xe00c w uart channel 1 transmit holding register undefined urxbuf0 0xd010 r uart channel 0 receive buffer register undefined urxbuf1 0xe010 r uart channel 1 receive buffer register undefined ubrdiv0 0xd014 r/w baud rate divisor register 0 0x00 ubrdiv1 0xe014 r/w baud rate divisor register 1 0x00 ucc1_0 0xd018 r/w uart0 control character register 1 0x00000000 ucc1_1 0xe018 r/w uart1 control character register 1 0x00000000 ucc2_0 0xd01c r/w uart0 control character register 2 0x00000000 ucc2_1 0xe01c r/w uart1 control character register 2 0x00000000 timers tmod 0x6000 r/w timer mode register 0x00000000 tdata0 0x6004 r/w timer 0 data register 0x00000000 tdata1 0x6008 r/w timer 1 data register 0x00000000 tcnt0 0x600c r/w timer 0 count register 0xffffffff tcnt1 0x6010 r/w timer 1 count register 0xffffffff
S3C4530A programmer 's model 2- 1 2 programmer s model overview S3C4530A was developed using the advanced arm7tdmi core designed by advanced risc machines, ltd. processor operating states from the programmer s point of view, the arm7tdmi can be in one of two states: ? arm state which executes 32-bit, word-aligned arm instructions. ? thumb state which operates with 16-bit, half-word-aligned thumb instructions. in this state, the pc uses bit 1 to select between alternate half-words. note transition between these two states does not affect the processor mode or the contents of the registers. switching state entering thumb state entry into thumb state can be achieved by executing a bx instruction with the state bit (bit 0) set in the operand register. transition to thumb state will also occur automatically on return from an exception (irq, fiq, undef, abort, swi etc.), if the exception was entered with the processor in thumb state. entering arm state entry into arm state happens: 1. on execution of the bx instruction with the state bit clear in the operand register. 2. on the processor taking an exception (irq, fiq, reset, undef, abort, swi etc.). in this case, the pc is placed in the exception mode s link register, and execution commences at the exception s vector address. memory formats arm7tdmi views memory as a linear collection of bytes numbered upwards from zero. bytes 0 to 3 hold the first stored word, bytes 4 to 7 the second and so on. arm7tdmi can treat words in memory as being stored either in big-endian or little-endian format.
programmer's model S3C4530A 2- 2 big-endian format in big-endian format, the most significant byte of a word is stored at the lowest numbered byte and the least significant byte at the highest numbered byte. byte 0 of the memory system is therefore connected to data lines 31 through 24. 8 4 0 24 31 5 9 15 8 7 0 word address 8 4 0 9 5 1 10 6 2 11 7 3 higher address lower address w most sign ificant byte is at lowest address w word is addressed by byte address of most signficant byte figure 2-1. big-endian addresses of bytes within words note the data locations in the external memory are different with figure 2-1 in the s3c4620. please refer to the chapter 4, system manager. little-endian format in little-endian format, the lowest numbered byte in a word is considered the word s least significant byte, and the highest numbered byte the most significant. byte 0 of the memory system is therefore connected to data lines 7 through 0. word address w most sign ificant byte is at lowest address w word is addressed by byte address of least signficant byte 8 4 0 24 31 16 23 15 8 7 0 11 7 3 10 6 2 9 5 1 8 4 0 higher address lower address figure 2-2. little-endian addresses of bytes words
S3C4530A programmer 's model 2- 3 instruction length instructions are either 32 bits long (in arm state) or 16 bits long (in thumb state). data types arm7tdmi supports byte (8-bit), half-word (16-bit) and word (32-bit) data types. words must be aligned to four- byte boundaries and half words to two-byte boundaries. operating modes arm7tdmi supports seven modes of operation: ? user (usr): the normal arm program execution state ? fiq (fiq): designed to support a data transfer or channel process ? irq (irq): used for general-purpose interrupt handling ? supervisor (svc): protected mode for the operating system ? abort mode (abt): entered after a data or instruction prefetch abort ? system (sys): a privileged user mode for the operating system ? undefined (und): entered when an undefined instruction is executed mode changes may be made under software control, or may be brought about by external interrupts or exception processing. most application programs will execute in user mode. the non-user modes known as privileged modes-are entered in order to service interrupts or exceptions, or to access protected resources.
programmer's model S3C4530A 2- 4 registers arm7tdmi has a total of 37 registers-31 general-purpose 32-bit registers and six status registers - but these cannot all be seen at once. the processor state and operating mode dictate which registers are available to the programmer. the arm state register set in arm state, 16 general registers and one or two status registers are visible at any one time. in privileged (non- user) modes, mode-specific banked registers are switched in. figure 2-3 shows which registers are available in each mode: the banked registers are marked with a shaded triangle. the arm state register set contains 16 directly accessible registers: r0 to r15. all of these except r15 are general-purpose, and may be used to hold either data or address values. in addition to these, there is a seventeenth register used to store status information. register 14 is used as the subroutine link register. this receives a copy of r15 when a branch and link (bl) instruction is executed. at all other times it may be treated as a general-purpose register. the corresponding banked registers r14_svc, r14_irq, r14_fiq, r14_abt and r14_und are similarly used to hold the return values of r15 when interrupts and exceptions arise, or when branch and link instructions are executed within interrupt or exception routines. register 15 holds the program counter (pc). in arm state, bits [1:0] of r15 are zero and bits [31:2] contain the pc. in thumb state, bit [0] is zero and bits [31:1] contain the pc. register 16 is the cpsr (current program status register). this contains condition code flags and the current mode bits. fiq mode has seven banked registers mapped to r8-14 (r8_fiq-r14_fiq). in arm state, many fiq handlers do not need to save any registers. user, irq, supervisor, abort and undefined each have two banked registers mapped to r13 and r14, allowing each of these modes to have a private stack pointer and link registers.
S3C4530A programmer 's model 2- 5 cpsr cpsr spsr_fiq cpsr spsr_svc cpsr spsr_abt cpsr spsr_irq cpsr spsr_und system & user fiq supervisor about irg undefined arm state program status register = banked register arm state general registers and program counter r0 r1 r2 r3 r4 r5 r6 r7 r10 r8 r9 r11 r12 r15 (pc) r13_und r14_und r0 r1 r2 r3 r4 r5 r6 r7 r10 r8 r9 r11 r12 r15 (pc) r13_irq r14_irq r0 r1 r2 r3 r4 r5 r6 r7 r10 r8 r9 r11 r12 r15 (pc) r13_abt r14_abt r10 r8 r9 r11 r12 r15 (pc) r13_svc r14_svc r0 r1 r2 r3 r4 r5 r6 r7 r0 r1 r2 r3 r4 r5 r6 r7 r8_fiq r9_fiq r10_fiq r11_fiq r12_fiq r13_fiq r14_fiq r15 (pc) r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 (pc) figure 2-3. register organization in arm state
programmer's model S3C4530A 2- 6 the thumb state register set the thumb state register set is a subset of the arm state set. the programmer has direct access to eight general registers, r0?r7, as well as the program counter (pc), a stack pointer register (sp), a link register (lr), and the cpsr. there are banked stack pointers, link registers and saved process status registers (spsrs) for each privileged mode. this is shown in figure 2-4. cpsr cpsr spsr_fiq cpsr spsr_svc cpsr spsr_abt cpsr spsr_irq cpsr spsr_und system & user fiq supervisor about irg undefined thumb state program status registers = banked register thumb state general registers and program counter r0 r1 r2 r3 r4 r5 r6 r7 sp lr pc sp_fiq lr_fiq r0 r1 r2 r3 r4 r5 r6 r7 pc sp_svg lr_svc r0 r1 r2 r3 r4 r5 r6 r7 pc sp_abt lr_abt r0 r1 r2 r3 r4 r5 r6 r7 pc sp_irq lr_irq r0 r1 r2 r3 r4 r5 r6 r7 pc sp_und lr_und r0 r1 r2 r3 r4 r5 r6 r7 pc figure 2-4. register organization in thumb state
S3C4530A programmer 's model 2- 7 the relationship between arm and thumb state registers the thumb state registers relate to the arm state registers in the following way: ? thumb state r0?r7 and arm state r0?r7 are identical ? thumb state cpsr and spsrs and arm state cpsr and spsrs are identical ? thumb state sp maps onto arm state r13 ? thumb state lr maps onto arm state r14 ? the thumb state program counter maps onto the arm state program counter (r15) this relationship is shown in figure 2-5. r0 r1 r2 r3 r4 r5 r6 r7 r0 r1 r2 r3 r5 r6 r7 r8 r9 r10 r11 r12 stack pointer (r13) link register (r14) program counter (r15) cpsr spsr stack pointer (sp) link register (lr) program counter (pc) cpsr spsr thumb state arm state lo-registers hi-registers r4 figure 2-5. mapping of thumb state registers onto arm state registers
programmer's model S3C4530A 2- 8 accessing hi-registers in thumb state in thumb state, registers r8?r15 (the hi registers) are not part of the standard register set. however, the assembly language programmer has limited access to them, and can use them for fast temporary storage. a value may be transferred from a register in the range r0?r7 (a lo register) to a hi register, and from a hi register to a lo register, using special variants of the mov instruction. hi register values can also be compared against or added to lo register values with the cmp and add instructions. for more information, refer to figure 3-34. the program status registers the arm7tdmi contains a current program status register (cpsr), plus five saved program status registers (spsrs) for use by exception handlers. these register s functions are: ? hold information about the most recently performed alu operation ? control the enabling and disabling of interrupts ? set the processor operating mode the arrangement of bits is shown in figure 2-6. n z c v . . . . . . i f t m4 m3 m2 m1 m0 31 30 29 28 27 26 25 24 8 7 6 5 4 3 2 1 0 condition code flags (reserved) control bits overflow carry/borrow/extend zero negative/less than mode bits state bit fiq disable frq disable figure 2-6. program status register format
S3C4530A programmer 's model 2- 9 the condition code flags the n, z, c and v bits are the condition code flags. these may be changed as a result of arithmetic and logical operations, and may be tested to determine whether an instruction should be executed. in arm state, all instructions may be executed conditionally: see table 3-2 for details. in thumb state, only the branch instruction is capable of conditional execution: see figure 3-46 for details. the control bits the bottom 8 bits of a psr (incorporating i, f, t and m[4:0]) are known collectively as the control bits. these will change when an exception arises. if the processor is operating in a privileged mode, they can also be manipulated by software. the t bit this reflects the operating state. when this bit is set, the processor is executing in thumb state, otherwise it is executing in arm state. this is reflected on the tbit external signal. note that the software must never change the state of the tbit in the cpsr. if this happens, the processor will enter an unpredictable state. interrupt disable bits the i and f bits are the interrupt disable bits. when set, these disable the irq and fiq interrupts respectively. the mode bits the m4, m3, m2, m1 and m0 bits (m[4:0]) are the mode bits. these determine the processor s operating mode, as shown in table 2-1. not all combinations of the mode bits define a valid processor mode. only those explicitly described shall be used. the user should be aware that if any illegal value is programmed into the mode bits, m[4:0], then the processor will enter an unrecoverable state. if this occurs, reset should be applied.
programmer's model S3C4530A 2- 10 table 2-1. psr mode. bit values m[4:0] mode visible thumb state registers visible arm state registers 10000 user r7..r0, lr, sp pc, cpsr r14..r0, pc, cpsr 10001 fiq r7..r0, lr_fiq, sp_fiq pc, cpsr, spsr_fiq r7..r0, r14_fiq..r8_fiq, pc, cpsr, spsr_fiq 10010 irq r7..r0, lr_irq, sp_irq pc, cpsr, spsr_irq r12..r0, r14_irq..r13_irq, pc, cpsr, spsr_irq 10011 supervisor r7..r0, lr_svc, sp_svc, pc, cpsr, spsr_svc r12..r0, r14_svc..r13_svc, pc, cpsr, spsr_svc 10111 abort r7..r0, lr_abt, sp_abt, pc, cpsr, spsr_abt r12..r0, r14_abt..r13_abt, pc, cpsr, spsr_abt 11011 undefined r7..r0 lr_und, sp_und, pc, cpsr, spsr_und r12..r0, r14_und..r13_und, pc, cpsr 11111 system r7..r0, lr, sp pc, cpsr r14..r0, pc, cpsr reserved bits the remaining bits in the psrs are reserved. when changing a psr s flag or control bits, you must ensure that these unused bits are not altered. also, your program should not rely on them containing specific values, since in future processors they may read as one or zero.
S3C4530A programmer 's model 2- 11 exceptions exceptions arise whenever the normal flow of a program has to be halted temporarily, for example to service an interrupt from a peripheral. before an exception can be handled, the current processor state must be preserved so that the original program can resume when the handler routine has finished. it is possible for several exceptions to arise at the same time. if this happens, they are dealt with in a fixed order. see exception priorities on page 2-14. action on entering an exception when handling an exception, the arm7tdmi: 1. preserves the address of the next instruction in the appropriate link register. if the exception has been entered from arm state, then the address of the next instruction is copied into the link register (that is, current pc + 4 or pc + 8 depending on the exception. see table 2-2 on for details). if the exception has been entered from thumb state, then the value written into the link register is the current pc offset by a value such that the program resumes from the correct place on return from the exception. this means that the exception handler need not determine which state the exception was entered from. for example, in the case of swi, movs pc, r14_svc will always return to the next instruction regardless of whether the swi was executed in arm or thumb state. 2. copies the cpsr into the appropriate spsr 3. forces the cpsr mode bits to a value which depends on the exception 4. forces the pc to fetch the next instruction from the relevant exception vector it may also set the interrupt disable flags to prevent otherwise unmanageable nesting of exceptions. if the processor is in thumb state when an exception occurs, it will automatically switch into arm state when the pc is loaded with the exception vector address. action on leaving an exception on completion, the exception handler: 1. moves the link register, minus an offset where appropriate, to the pc. (the offset will vary depending on the type of exception.) 2. copies the spsr back to the cpsr 3. clears the interrupt disable flags, if they were set on entry note an explicit switch back to thumb state is never needed, since restoring the cpsr from the spsr automatically sets the t bit to the value it held immediately prior to the exception.
programmer's model S3C4530A 2- 12 exception entry/exit summary table 2-2 summarizes the pc value preserved in the relevant r14 on exception entry, and the recommended instruction for exiting the exception handler. table 2-2. exception entry/exit return instruction previous state notes arm r14_x thumb r14_x bl mov pc, r14 pc + 4 pc + 2 1 swi movs pc, r14_svc pc + 4 pc + 2 1 udef movs pc, r14_und pc + 4 pc + 2 1 fiq subs pc, r14_fiq, #4 pc + 4 pc + 4 2 irq subs pc, r14_irq, #4 pc + 4 pc + 4 2 pabt subs pc, r14_abt, #4 pc + 4 pc + 4 1 dabt subs pc, r14_abt, #8 pc + 8 pc + 8 3 reset na ? ? 4 notes: 1. where pc is the address of the bl/swi/undefined instruction fetch which had the prefetch abort. 2. where pc is the address of the instruction which did not get executed since the fiq or irq took priority. 3. where pc is the address of the load or store instruction which generated the data abort. 4. the value saved in r14_svc upon reset is unpredictable. fiq the fiq (fast interrupt request) exception is designed to support a data transfer or channel process, and in arm state has sufficient private registers to remove the need for register saving (thus minimizing the overhead of context switching). fiq is externally generated by taking the nfiq input low. this input can except either synchronous or asynchronous transitions, depending on the state of the isync input signal. when isync is low, nfiq and nirq are considered asynchronous, and a cycle delay for synchronization is incurred before the interrupt can affect the processor flow. irrespective of whether the exception was entered from arm or thumb state, a fiq handler should leave the interrupt by executing subs pc,r14_fiq,#4 fiq may be disabled by setting the cpsr's f flag (but note that this is not possible from user mode). if the f flag is clear, arm7tdmi checks for a low level on the output of the fiq synchroniser at the end of each instruction.
S3C4530A programmer 's model 2- 13 irq the irq (interrupt request) exception is a normal interrupt caused by a low level on the nirq input. irq has a lower priority than fiq and is masked out when a fiq sequence is entered. it may be disabled at any time by setting the i bit in the cpsr, though this can only be done from a privileged (non-user) mode. irrespective of whether the exception was entered from arm or thumb state, an irq handler should return from the interrupt by executing subs pc,r14_irq,#4 abort an abort indicates that the current memory access cannot be completed. it can be signalled by the external abort input. arm7tdmi checks for the abort exception during memory access cycles. there are two types of abort: ? prefetch abort: occurs during an instruction prefetch. ? data abort: occurs during a data access. if a prefetch abort occurs, the prefetched instruction is marked as invalid, but the exception will not be taken until the instruction reaches the head of the pipeline. if the instruction is not executed - for example because a branch occurs while it is in the pipeline - the abort does not take place. if a data abort occurs, the action taken depends on the instruction type: ? single data transfer instructions (ldr, str) write back modified base registers: the abort handler must be aware of this. ? the swap instruction (swp) is aborted as though it had not been executed. ? block data transfer instructions (ldm, stm) complete. if write-back is set, the base is updated. if the instruction would have overwritten the base with data (ie it has the base in the transfer list), the overwriting is prevented. all register overwriting is prevented after an abort is indicated, which means in particular that r15 (always the last register to be transferred) is preserved in an aborted ldm instruction. the abort mechanism allows the implementation of a demand paged virtual memory system. in such a system the processor is allowed to generate arbitrary addresses. when the data at an address is unavailable, the memory management unit (mmu) signals an abort. the abort handler must then work out the cause of the abort, make the requested data available, and retry the aborted instruction. the application program needs no knowledge of the amount of memory available to it, nor is its state in any way affected by the abort. after fixing the reason for the abort, the handler should execute the following irrespective of the state (arm or thumb): subs pc,r14_abt,#4 ; for a prefetch abort, or subs pc,r14_abt,#8 ; for a data abort this restores both the pc and the cpsr, and retries the aborted instruction.
programmer's model S3C4530A 2- 14 software interrupt the software interrupt instruction (swi) is used for entering supervisor mode, usually to request a particular supervisor function. a swi handler should return by executing the following irrespective of the state (arm or thumb): mov pc,r14_svc this restores the pc and cpsr, and returns to the instruction following the swi. note nfiq, nirq, isync, lock, bigend, and abort pins exist only in the arm7tdmi cpu core. undefined instruction when arm7tdmi comes across an instruction which it cannot handle, it takes the undefined instruction trap. this mechanism may be used to extend either the thumb or arm instruction set by software emulation. after emulating the failed instruction, the trap handler should execute the following irrespective of the state (arm or thumb): movs pc,r14_und this restores the cpsr and returns to the instruction following the undefined instruction. exception vectors the following table shows the exception vector addresses. table 2-3. exception vectors address exception mode in entry 0x00000000 reset supervisor 0x00000004 undefined instruction undefined 0x00000008 software interrupt supervisor 0x0000000c abort (prefetch) abort 0x00000010 abort (data) abort 0x00000014 reserved reserved 0x00000018 irq irq 0x0000001c fiq fiq
S3C4530A programmer s model 2- 15 exception priorities when multiple exceptions arise at the same time, a fixed priority system determines the order in which they are handled: highest priority: 1. reset 2. data abort 3. fiq 4. irq 5. prefetch abort lowest priority: 6. undefined instruction, software interrupt. not all exceptions can occur at once: undefined instruction and software interrupt are mutually exclusive, since they each correspond to particular (non-overlapping) decoding of the current instruction. if a data abort occurs at the same time as a fiq, and fiqs are enabled (ie the cpsr's f flag is clear), arm7tdmi enters the data abort handler and then immediately proceeds to the fiq vector. a normal return from fiq will cause the data abort handler to resume execution. placing data abort at a higher priority than fiq is necessary to ensure that the transfer error does not escape detection. the time for this exception entry should be added to worst-case fiq latency calculations.
programmer s model S3C4530A 2- 16 interrupt latencies the worst case latency for fiq, assuming that it is enabled, consists of the longest time the request can take to pass through the synchroniser ( tsyncmax if asynchronous), plus the time for the longest instruction to complete ( tldm , the longest instruction is an ldm which loads all the registers including the pc), plus the time for the data abort entry ( texc ), plus the time for fiq entry ( tfiq ). at the end of this time arm7tdmi will be executing the instruction at 0x1c. tsyncmax is 3 processor cycles, tldm is 20 cycles, texc is 3 cycles, and tfiq is 2 cycles. the total time is therefore 28 processor cycles. this is just over 1.4 microseconds in a system which uses a continuous 20 mhz processor clock. the maximum irq latency calculation is similar, but must allow for the fact that fiq has higher priority and could delay entry into the irq handling routine for an arbitrary length of time. the minimum latency for fiq or irq consists of the shortest time the request can take through the synchroniser (tsyncmin) plus tfiq . this is 4 processor cycles. reset when the nreset signal goes low, arm7tdmi abandons the executing instruction and then continues to fetch instructions from incrementing word addresses. when nreset goes high again, arm7tdmi: 1. overwrites r14_svc and spsr_svc by copying the current values of the pc and cpsr into them. the value of the saved pc and spsr is not defined. 2. fo rces m[4:0] to 10011 (supervisor mode), sets the i and f bits in the cpsr, and clears the cpsr's t bit. 3. forces the pc to fetch the next instruction from address 0x00. 4. execution resumes in arm state.
S3C4530A instructio n set 3- 1 3 instruction set instruction set summay this chapter describes the arm instruction set and the thumb instruction set in the arm7tdmi core. format summary the arm instruction set formats are shown below. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 data processing/ psr transfer multiply multiply long single data swap branch and exchange halfword data transfer: register offset halfword data transfer: immediate offset block data transfer branch coprocessor data transfer coprocessor data operation coprocessor register transfer software interrupt undefined single data transfer cond 1 1 1 1 ignored by processor cond 1 1 1 0 crn rd cp opc l cp# cp# 1 crm cond 1 1 1 0 crn crd cp opc cp# cp# 0 crm cond 1 1 0 p u n w l rn crd cp# offset cond 1 0 1 l offset cond 1 0 0 p u s w l rn register list cond 0 1 1 1 cond 0 1 1 p u b w l rn rd offset cond 0 0 0 p u 1 w l rn rd offset 1 s h 1 offset cond 0 0 0 p u 0 w l rn rd 0 0 0 0 1 s h 1 rm cond 0 0 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 rn cond 0 0 0 1 0 b 0 0 rn rd rm 0 0 0 0 1 0 0 1 cond 0 0 0 0 1 u a s rdhi rnlo rn 1 0 0 1 rm cond 0 0 0 0 0 0 a s rd rn rs 1 0 0 1 rm cond 0 0 1 opcode s rn rd operand2 figure 3-1. arm instruction set format note some instruction codes are not defined but do not cause the undefined instruction trap to be taken, for instance a multiply instruction with bit 6 changed to a 1. these instructions should not be used, as their action may change in future arm implementations.
instruction set s3c 4530a 3- 2 instruction summary table 3-1. the arm instruction set mnemonic instruction action adc add with carry rd: = rn + op2 + carry add add rd: = rn + op2 and and rd: = rn and op2 b branch r15: = address bic bit clear rd: = rn and not op2 bl branch with link r14: = r15, r15: = address bx branch and exchange r15: = rn, t bit: = rn[0] cdp coprocessor data processing (coprocessor-specific) cmn compare negative cpsr flags: = rn + op2 cmp compare cpsr flags: = rn - op2 eor exclusive or rd: = (rn and not op2) or (op2 and not rn) ldc load coprocessor from memory coprocessor load ldm load multiple registers stack manipulation (pop) ldr load register from memory rd: = (address) mcr move cpu register to coprocessor register crn: = rrn {crm} mla multiply accumulate rd: = (rm * rs) + rn mov move register or constant rd: = op2 mrc move from coprocessor register to cpu register rn: = crn {crm} mrs move psr status/flags to register rn: = psr msr move register to psr status/flags psr: = rm mul multiply rd: = rm * rs mvn move negative register rd: = 0xffffffff eor op2
S3C4530A instructio n set 3- 3 table 3-1. the arm instruction set (continued) mnemonic instruction action orr or rd: = rn or op2 rsb reverse subtract rd: = op2 - rn rsc reverse subtract with carry rd: = op2 - rn-1 + carry sbc subtract with carry rd: = rn - op2-1 + carry stc store coprocessor register to memory address: = crn stm store multiple stack manipulation (push) str store register to memory

: = rd sub subtract rd: = rn - op2 swi software interrupt os call swp swap register with memory rd: = [rn], [rn] := rm teq test bit-wise equality cpsr flags: = rn eor op2 tst test bits cpsr flags: = rn and op2
instruction set s3c 4530a 3- 4 the condition field in arm state, all instructions are conditionally executed according to the state of the cpsr condition codes and the instruction s condition field. this field (bits 31:28) determines the circumstances under which an instruction is to be executed. if the state of the c, n, z and v flags fulfils the conditions encoded by the field, the instruction is executed, otherwise it is ignored. there are sixteen possible conditions, each represented by a two-character suffix that can be appended to the instruction s mnemonic. for example, a branch (b in assembly language) becomes beq for " branch if " equal " , which means the branch will only be taken if the z flag is set. in practice, fifteen different conditions may be used: these are listed in table 3-2. the sixteenth (1111) is reserved, and must not be used. in the absence of a suffix, the condition field of most instructions is set to ?always" (suffix al). this means the instruction will always be executed regardless of the cpsr condition codes. table 3-2. condition code summary code suffix flags meaning 0000 eq z set equal 0001 ne z clear not equal 0010 cs c set unsigned higher or same 0011 cc c clear unsigned lower 0100 mi n set negative 0101 pl n clear positive or zero 0110 vs v set overflow 0111 vc v clear no overflow 1000 hi c set and z clear unsigned higher 1001 ls c clear or z set unsigned lower or same 1010 ge n equals v greater or equal 1011 lt n not equal to v less than 1100 gt z clear and (n equals v) greater than 1101 le z set or (n not equal to v) less than or equal 1110 al (ignored) always
S3C4530A instructio n set 3- 5 branch and exchange (bx) this instruction is only executed if the condition is true. the various conditions are defined in table 3-2. this instruction performs a branch by copying the contents of a general register, rn, into the program counter, pc. the branch causes a pipeline flush and refill from the address specified by rn. this instruction also permits the instruction set to be exchanged. when the instruction is executed, the value of rn[0] determines whether the instruction stream will be decoded as arm or thumb instructions. 31 24 27 19 15 8 7 0 0 0 0 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 cond rn 28 16 11 12 23 20 4 3 [3:0] operand register if bit0 of rn = 1, subsequent instructions decoded as thumb instructions if bit0 of rn =0, subsequent instructions decoded as arm instructions [31:28] condition field figure 3-2. branch and exchange instructions instruction cycle times the bx instruction takes 2s + 1n cycles to execute, where s and n are defined as sequential (s-cycle) and non- sequential (n-cycle), respectively. assembler syntax bx - branch and exchange. bx {cond} rn {cond} two character condition mnemonic. see table 3-2. rn is an expression evaluating to a valid register number. using r15 as an operand if r15 is used as an operand, the behaviour is undefined.
instruction set s3c 4530a 3- 6 examples adr r0, into_thumb + 1 ; generate branch target address ; and set bit 0 high - hence ; arrive in thumb state. bx r0 ; branch and change to thumb ; state. code16 ; assemble subsequent code as into_thumb ; thumb instructions adr r5, back_to_arm ; generate branch target to word aligned address ; - hence bit 0 is low and so change back to arm state. bx r5 ; branch and change back to arm state. align ; word align code32 ; assemble subsequent code as arm instructions back_to_arm
S3C4530A instructio n set 3- 7 branch and branch with link (b, bl) the instruction is only executed if the condition is true. the various conditions are defined table 3-2. the instruction encoding is shown in figure 3-3, below. 31 24 27 cond offset 28 23 [24] link bit 0 = branch 1 = branch with link [31:28] condition field 25 101 l 0 figure 3-3. branch instructions branch instructions contain a signed 2?s complement 24 bit offset. this is shifted left two bits, sign extended to 32 bits, and added to the pc. the instruction can therefore specify a branch of +/- 32mbytes. the branch offset must take account of the pre-fetch operation, which causes the pc to be 2 words (8 bytes) ahead of the current instruction. the link bit branch with link (bl) writes the old pc into the link register (r14) of the current bank. the pc value written into r14 is adjusted to allow for the pre-fetch, and contains the address of the instruction following the branch and link instruction. note that the cpsr is not saved with the pc and r14[1:0] are always cleared. to return from a routine called by branch with link use mov pc,r14 if the link register is still valid or ldm rn!,{..pc} if the link register has been saved onto a stack pointed to by rn. instruction cycle times branch and branch with link instructions take 2s + 1n incremental cycles, where s and n are defined as sequential (s-cycle) and internal (i-cycle).
instruction set s3c 4530a 3- 8 assembler syntax items in {} are optional. items in < > must be present. b{l}{cond} { l} used to request the branch with link form of the instruction. if absent, r14 will not be affected by the instruction. { cond} a two-character mnemonic as shown in table 3-2. if absent then al (always) will be used. the destination. the assembler calculates the offset. examples here bal here ; assembles to 0xeafffffe (note effect of pc offset). b there ; always condition used as default. cmp r1,#0 ; compare r1 with zero and branch to fred ; if r1 was zero, otherwise continue. beq fred ; continue to next instruction. bl sub+rom ; call subroutine at computed address. adds r1,#1 ; add 1 to register 1, setting cpsr flags ; on the result then call subroutine if blcc sub ; the c flag is clear, which will be the ; case unless r1 held 0xffffffff.
S3C4530A instructio n set 3- 9 data processing the data processing instruction is only executed if the condition is true. the conditions are defined in table 3-2. the instruction encoding is shown in figure 3-4. 31 24 27 19 15 cond operand2 28 16 11 12 21 [15:12] destination register 0 = branch 1 = branch with link [19:16] 1st operand register 0 = branch 1 = branch with link [20] set condition codes 0 = do not after condition codes 1 = set condition codes [24:21] operation code 0000 = and-rd: = op1 and op2 0001 = eor-rd: = op1 eor op2 0010 = sub-rd: = op1-op2 0011 = rsb-rd: = op2-op1 0100 = add-rd: = op1+op2 0101 = adc-rd: = op1+op2+c 0110 = sbc-rd: = op1-op2+c-1 0111 = rsc-rd: = op2-op1+c-1 1000 = tst-set condition codes on op1 and op2 1001 = teo-set condition codes on op1 eor op2 1010 = cmp-set condition codes on op1-op2 1011 = smn-set condition codes on op1+op2 1100 = orr-rd: = op1 or op2 1101 = mov-rd: =op2 1110 = bic-rd: = op1 and not op2 1111 = mvn-rd: = not op2 [25] immediate operand 0 = operand 2 is a register 1 = operand 2 is an immediate value [11:0] operand 2 type selection [31:28] condition field 26 25 00 l 20 opcode s rn rd 0 rotate shift rm [3:0] 2nd operand register [11:4] shift applied to rm 3 11 0 4 8 11 0 7 imm [7:0] unsigned 8 bit immediate value [11:8] shift applied to imm figure 3-4. data processing instructions
instruction set s3c 4530a 3- 10 the instruction produces a result by performing a specified arithmetic or logical operation on one or two operands. the first operand is always a register (rn). the second operand may be a shifted register (rm) or a rotated 8 bit immediate value (imm) according to the value of the i bit in the instruction. the condition codes in the cpsr may be preserved or updated as a result of this instruction, according to the value of the s bit in the instruction. certain operations (tst, teq, cmp, cmn) do not write the result to rd. they are used only to perform tests and to set the condition codes on the result and always have the s bit set. the instructions and their effects are listed in table 3-3.
S3C4530A instructio n set 3- 11 cpsr flags the data processing operations may be classified as logical or arithmetic. the logical operations (and, eor, tst, teq, orr, mov, bic, mvn) perform the logical action on all corresponding bits of the operand or operands to produce the result. if the s bit is set (and rd is not r15, see below) the v flag in the cpsr will be unaffected, the c flag will be set to the carry out from the barrel shifter (or preserved when the shift operation is lsl #0), the z flag will be set if and only if the result is all zeros, and the n flag will be set to the logical value of bit 31 of the result. table 3-3. arm data processing instructions assembler mnemonic opcode action and 0000 operand1 and operand2 eor 0001 operand1 eor operand2 sub 0010 operand1 - operand2 rsb 0011 operand2 - operand1 add 0100 operand1 + operand2 adc 0101 operand1 + operand2 + carry sbc 0110 operand1 - operand2 + carry - 1 rsc 0111 operand2 - operand1 + carry - 1 tst 1000 as and, but result is not written teq 1001 as eor, but result is not written cmp 1010 as sub, but result is not written cmn 1011 as add, but result is not written orr 1100 operand1 or operand2 mov 1101 operand2 (operand1 is ignored) bic 1110 operand1 and not operand2 (bit clear) mvn 1111 not operand2 (operand1 is ignored) the arithmetic operations (sub, rsb, add, adc, sbc, rsc, cmp, cmn) treat each operand as a 32 bit integer (either unsigned or 2's complement signed, the two are equivalent). if the s bit is set (and rd is not r15) the v flag in the cpsr will be set if an overflow occurs into bit 31 of the result; this may be ignored if the operands were considered unsigned, but warns of a possible error if the operands were 2's complement signed. the c flag will be set to the carry out of bit 31 of the alu, the z flag will be set if and only if the result was zero, and the n flag will be set to the value of bit 31 of the result (indicating a negative result if the operands are considered to be 2's complement signed).
instruction set s3c 4530a 3- 12 shifts when the second operand is specified to be a shifted register, the operation of the barrel shifter is controlled by the shift field in the instruction. this field indicates the type of shift to be performed (logical left or right, arithmetic right or rotate right). the amount by which the register should be shifted may be contained in an immediate field in the instruction, or in the bottom byte of another register (other than r15). the encoding for the different shift types is shown in figure 3-5. 0 [6:5] shift type 00 = logical left 01 = logical right 10 = arithmetic right 11 = rotate right [11:7] shift amount 5 bit unsigned integer [6:5] shift type 00 = logical left 01 = logical right 10 = arithmetic right 11 = rotate right [11:8] shift register shift amount specified in bottom-byte of rs 4 5 6 7 11 1 4 5 6 7 11 8 0 rs figure 3-5. arm shift operations instruction specified shift amount when the shift amount is specified in the instruction, it is contained in a 5 bit field which may take any value from 0 to 31. a logical shift left (lsl) takes the contents of rm and moves each bit by the specified amount to a more significant position. the least significant bits of the result are filled with zeros, and the high bits of rm which do not map into the result are discarded, except that the least significant discarded bit becomes the shifter carry output which may be latched into the c bit of the cpsr when the alu operation is in the logical class (see above). for example, the effect of lsl #5 is shown in figure 3-6. 31 27 26 contents of rm value of operand 2 carry out 0 0 0 0 0 0 figure 3-6. logical shift left note lsl #0 is a special case, where the shifter carry out is the old value of the cpsr c flag. the contents of rm are used directly as the second operand. a logical shift right (lsr) is similar, but the contents of rm are moved to less significant positions in the result. lsr #5 has the effect shown in figure 3-7 .
S3C4530A instructio n set 3- 13 31 contents of rm value of operand 2 0 carry out 4 5 0 0 0 0 0 figure 3-7. logical shift right the form of the shift field which might be expected to correspond to lsr #0 is used to encode lsr #32, which has a zero result with bit 31 of rm as the carry output. logical shift right zero is redundant as it is the same as logical shift left zero, so the assembler will convert lsr #0 (and asr #0 and ror #0) into lsl #0, and allow lsr #32 to be specified. an arithmetic shift right (asr) is similar to logical shift right, except that the high bits are filled with bit 31 of rm instead of zeros. this preserves the sign in 2's complement notation. for example, asr #5 is shown in figure 3- 8. 31 contents of rm value of operand 2 0 carry out 4 5 30 figure 3-8. arithmetic shift right the form of the shift field which might be expected to give asr #0 is used to encode asr #32. bit 31 of rm is again used as the carry output, and each bit of operand 2 is also equal to bit 31 of rm. the result is therefore all ones or all zeros, according to the value of bit 31 of rm.
instruction set s3c 4530a 3- 14 rotate right (ror) operations reuse the bits which overshoot in a logical shift right operation by reintroducing them at the high end of the result, in place of the zeros used to fill the high end in logical right operations. for example, ror #5 is shown in figure 3-9. the form of the shift field which might be expected to give ror #0 is 31 contents of rm value of operand 2 0 carry out 4 5 figure 3-9. rotate right used to encode a special function of the barrel shifter, rotate right extended ( rrx). this is a rotate right by one bit position of the 33 bit quantity formed by appending the cpsr c flag to the most significant end of the contents of rm as shown in figure 3-10. 31 contents of rm value of operand 2 0 1 carry out c in figure 3-10. rotate right extended
S3C4530A instructio n set 3- 15 register specified shift amount only the least significant byte of the contents of rs is used to determine the shift amount. rs can be any general register other than r15. if this byte is zero, the unchanged contents of rm will be used as the second operand, and the old value of the cpsr c flag will be passed on as the shifter carry output. if the byte has a value between 1 and 31, the shifted result will exactly match that of an instruction specified shift with the same value and shift operation. if the value in the byte is 32 or more, the result will be a logical extension of the shift described above: 1. lsl by 32 has result zero, carry out equal to bit 0 of rm. 2. lsl by more than 32 has result zero, carry out zero. 3. lsr by 32 has result zero, carry out equal to bit 31 of rm. 4. lsr by more than 32 has result zero, carry out zero. 5. asr by 32 or more has result filled with and carry out equal to bit 31 of rm. 6. ror by 32 has result equal to rm, carry out equal to bit 31 of rm. 7. ror by n where n is greater than 32 will give the same result and carry out as ror by n-32; therefore repeatedly subtract 32 from n until the amount is in the range 1 to 32 and see above. note the zero in bit 7 of an instruction with a register controlled shift is compulsory; a one in this bit will cause the instruction to be a multiply or undefined instruction.
instruction set s3c 4530a 3- 16 immediate operand rotates the immediate operand rotate field is a 4 bit unsigned integer which specifies a shift operation on the 8 bit immediate value. this value is zero extended to 32 bits, and then subject to a rotate right by twice the value in the rotate field. this enables many common constants to be generated, for example all powers of 2. writing to r15 when rd is a register other than r15, the condition code flags in the cpsr may be updated from the alu flags as described above. when rd is r15 and the s flag in the instruction is not set the result of the operation is placed in r15 and the cpsr is unaffected. when rd is r15 and the s flag is set the result of the operation is placed in r15 and the spsr corresponding to the current mode is moved to the cpsr. this allows state changes which atomically restore both pc and cpsr. this form of instruction should not be used in user mode. using r15 as an operand if r15 (the pc) is used as an operand in a data processing instruction the register is used directly. the pc value will be the address of the instruction, plus 8 or 12 bytes due to instruction prefetching. if the shift amount is specified in the instruction, the pc will be 8 bytes ahead. if a register is used to specify the shift amount the pc will be 12 bytes ahead. teq, tst, cmp and cmn opcodes note teq, tst, cmp and cmn do not write the result of their operation but do set flags in the cpsr. an assembler should always set the s flag for these instructions even if this is not specified in the mnemonic. the teqp form of the teq instruction used in earlier arm processors must not be used: the psr transfer operations should be used instead. the action of teqp in the arm7tdmi is to move spsr_ to the cpsr if the processor is in a privileged mode and to do nothing if in user mode.
S3C4530A instructio n set 3- 17 instruction cycle times data processing instructions vary in the number of incremental cycles taken as follows: table 3-4. incremental cycle times processing type cycles normal data processing 1s data processing with register specified shift 1s + 1i data processing with pc written 2s + 1n data processing with register specified shift and pc written 2s + 1n + 1i note: s, n and i are as defined sequential (s-cycle), non-sequential (n-cycle), and internal (i-cycle) respectively. assembler syntax ? mov,mvn (single operand instructions). {cond}{s} rd, ? cmp,cmn,teq,tst (instructions which do not produce a result). {cond} rn, ? and,eor,sub,rsb,add,adc,sbc,rsc,orr,bic {cond}{s} rd,rn, where: rm{,} or,<#expression> { cond} a two-character condition mnemonic. see table 3-2. { s} set condition codes if s present (implied for cmp, cmn, teq, tst). rd, rn and rm expressions evaluating to a register number. <#expression> if this is used, the assembler will attempt to generate a shifted immediate 8-bit field to match the expression. if this is impossible, it will give an error. or #expression, or rrx (rotate right one bit with extend). s asl, lsl, lsr, asr, ror. (asl is a synonym for lsl, they assemble to the same code.)
instruction set s3c 4530a 3- 18 examples addeq r2,r4,r5 ; if the z flag is set make r2: = r4 + r5 teqs r4,#3 ; test r4 for equality with 3. ; (the s is in fact redundant as the ; assembler inserts it automatically.) sub r4,r5,r7,lsr r2 ; logical right shift r7 by the number in ; the bottom byte of r2, subtract result ; from r5, and put the answer into r4. mov pc,r14 ; return from subroutine. movs pc,r14 ; return from exception and restore cpsr ; from spsr_mode.
S3C4530A instructio n set 3- 19 psr transfer (mrs, msr) the instruction is only executed if the condition is true. the various conditions are defined in table 3-2. the mrs and msr instructions are formed from a subset of the data processing operations and are implemented using the teq, tst, cmn and cmp instructions without the s flag set. the encoding is shown in figure 3-11. these instructions allow access to the cpsr and spsr registers. the mrs instruction allows the contents of the cpsr or spsr_ to be moved to a general register. the msr instruction allows the contents of a general register to be moved to the cpsr or spsr_ register. the msr instruction also allows an immediate value or register contents to be transferred to the condition code flags (n,z,c and v) of cpsr or spsr_ without affecting the control bits. in this case, the top four bits of the specified register contents or 32 bit immediate value are written to the top four bits of the relevant psr. operand restrictions ? in user mode, the control bits of the cpsr are protected from change, so only the condition code flags of the cpsr can be changed. in other (privileged) modes the entire cpsr can be changed. ? note that the software must never change the state of the t bit in the cpsr. if this happens, the processor will enter an unpredictable state. ? the spsr register which is accessed depends on the mode at the time of execution. for example, only spsr_fiq is accessible when the processor is in fiq mode. ? you must not specify r15 as the source or destination register. ? also, do not attempt to access an spsr in user mode, since no such register exists.
instruction set s3c 4530a 3- 20 mrs (transfer register contents or immediate value to psr flag bits only) cond soucer operand pd 101001111 31 22 27 28 11 12 21 23 i 10 00 26 25 24 0 cond 00000000 00010 pd 101001111 31 22 27 28 11 12 21 23 rm mrs (transfer register contents to psr) 4 3 0 cond 000000000000 00010 rd ps 001111 31 22 27 15 28 16 11 12 21 23 mrs (transfer psr contents to a register) 0 [3:0] source register [22] destination psr 0 = cpsr 1 = spsr_ [31:28] condition field [15:21] destination register [19:16] source psr 0 = cpsr 1 = spsr_ [31:28] condition field [3:0] source register [11:4] source operand is an immediate value [7:0] unsigned 8 bit immediate value [11:8] shift applied to imm [22] destination psr 0 = cpsr 1 = spsr_ [25] immediate operand 0 = source operand is a register 1 = spsr_ [11:0] source operand [31:28] condition field 00000000 rm 11 4 3 0 rotate imm 11 0 8 7 figure 3-11. psr transfer
S3C4530A instructio n set 3- 21 reserved bits only twelve bits of the psr are defined in arm7tdmi (n, z, c, v, i, f, t & m[4:0]); the remaining bits are reserved for use in future versions of the processor. refer to figure 2-6 for a full description of the psr bits. to ensure the maximum compatibility between arm7tdmi programs and future processors, the following rules should be observed: ? the reserved bits should be preserved when changing the value in a psr. ? programs should not rely on specific values from the reserved bits when checking the psr status, since they may read as one or zero in future processors. a read-modify-write strategy should therefore be used when altering the control bits of any psr register; this involves transferring the appropriate psr register to a general register using the mrs instruction, changing only the relevant bits and then transferring the modified value back to the psr register using the msr instruction. examples the following sequence performs a mode change: mrs r0,cpsr ; take a copy of the cpsr. bic r0,r0,#0x1f ; clear the mode bits. orr r0,r0,#new_mode ; select new mode msr cpsr,r0 ; write back the modified cpsr. when the aim is simply to change the condition code flags in a psr, a value can be written directly to the flag bits without disturbing the control bits. the following instruction sets the n, z, c and v flags: msr cpsr_flg,#0xf0000000 ; set all the flags regardless of their previous state ; (does not affect any control bits). no attempt should be made to write an 8 bit immediate value into the whole psr since such an operation cannot preserve the reserved bits. instruction cycle times psr transfers take 1s incremental cycles, where s is defined as sequential (s-cycle).
instruction set s3c 4530a 3- 22 assembler syntax ? mrs - transfer psr contents to a register mrs{cond} rd, ? msr - transfer register contents to psr msr{cond} ,rm ? msr - transfer register contents to psr flag bits only msr{cond} ,rm the most significant four bits of the register contents are written to the n,z,c & v flags respectively. ? msr - transfer immediate value to psr flag bits only msr{cond} , <#expression> the expression should symbolise a 32 bit value of which the most significant four bits are written to the n, z, c and v flags respectively. key: { cond} two-character condition mnemonic. see table 3-2. rd and rm expressions evaluating to a register number other than r15 cpsr, cpsr_all, spsr or spsr_all. (cpsr and cpsr_all are synonyms as are spsr and spsr_all) cpsr_flg or spsr_flg <#expression> where this is used, the assembler will attempt to generate a shifted immediate 8-bit field to match the expression. if this is impossible, it will give an error. examples in user mode the instructions behave as follows: msr cpsr_all,rm ; cpsr[31:28] ? rm[31:28] msr cpsr_flg,rm ; cpsr[31:28] ? rm[31:28] msr cpsr_flg,#0xa0000000 ; cpsr[31:28] ? 0xa (set n, c; clear z, v) mrs rd,cpsr ; rd[31:0] ? cpsr[31:0] in privileged modes the instructions behave as follows: msr cpsr_all,rm ; cpsr[31:0] ? rm[31:0] msr cpsr_flg,rm ; cpsr[31:28] ? rm[31:28] msr cpsr_flg,#0x50000000 ; cpsr[31:28] ? 0x5 (set z, v; clear n, c) msr spsr_all,rm ; spsr_[31:0] ? rm[31:0] msr spsr_flg,rm ; spsr_[31:28] ? rm[31:28] msr spsr_flg,#0xc0000000 ; spsr_[31:28] ? 0xc (set n, z; clear c, v) mrs rd,spsr ; rd[31:0] ? spsr_[31:0]
S3C4530A instructio n set 3- 23 multiply and multiply-accumulate (mul, mla) the instruction is only executed if the condition is true. the various conditions are defined in table 3-2. the instruction encoding is shown in figure 3-12. the multiply and multiply-accumulate instructions use an 8 bit booth's algorithm to perform integer multiplication. 31 27 19 15 cond 28 16 11 12 21 20 s rd rn [15:12][11:8][3:0] operand registers [19:16] destination register [20] set condition code 0 = do not alter condition codes 1 = set condition codes [21] accumulate 0 = multiply only 1 = multiply and accumulate [31:28] condition field 22 1 0 0 1 rs rm a 0 0 0 0 0 0 8 7 4 3 0 figure 3-12. multiply instructions the multiply form of the instruction gives rd: = rm * rs. rn is ignored, and should be set to zero for compatibility with possible future upgrades to the instruction set. the multiply-accumulate form gives rd: = rm * rs + rn, which can save an explicit add instruction in some circumstances. both forms of the instruction work on operands which may be considered as signed (2? complement) or unsigned integers. the results of a signed multiply nd of an unsigned multiply of 32 bit operands differ only in the upper 32 bits-the low 32 bits of the signed and unsigned results are identical. as these instructions only produce the low 32 bits of a multiply, they can be used for both signed and unsigned multiplies. for example consider the multiplication of the operands: operand a operand b result 0xfffffff6 0x0000001 0xffffff38 if the operands are interpreted as signed operand a has the value -10, operand b has the value 20, and the result is -200 which is correctly represented as 0xffffff38. if the operands are interpreted as unsigned operand a has the value 4294967286, operand b has the value 20 and the result is 85899345720, which is represented as 0x13ffffff38, so the least significant 32 bits are 0xffffff38. operand restrictions the destination register rd must not be the same as the operand register rm. r15 must not be used as an operand or as the destination register. all other register combinations will give correct results, and rd, rn and rs may use the same register when required.
instruction set s3c 4530a 3- 24 cpsr flags setting the cpsr flags is optional, and is controlled by the s bit in the instruction. the n (negative) and z (zero) flags are set correctly on the result (n is made equal to bit 31 of the result, and z is set if and only if the result is zero). the c (carry) flag is set to a meaningless value and the v (overflow) flag is unaffected. instruction cycle times mul takes 1s + mi and mla 1s + (m+1)i cycles to execute, where s and i are defined as sequential (s-cycle) and internal (i-cycle), respectively. m the number of 8 bit multiplier array cycles is required to complete the multiply, which is controlled by the value of the multiplier operand specified by rs. its possible values are as follows 1 if bits [32:8] of the multiplier operand are all zero or all one. 2 if bits [32:16] of the multiplier operand are all zero or all one. 3 if bits [32:24] of the multiplier operand are all zero or all one. 4 in all other cases. assembler syntax mul{cond}{s} rd,rm,rs mla{cond}{s} rd,rm,rs,rn { cond} two-character condition mnemonic. see table 3-2. { s} set condition codes if s present rd, rm, rs and rn expressions evaluating to a register number other than r15. examples mul r1,r2,r3 ; r1: = r2 * r3 mlaeqs r1,r2,r3,r4 ; conditionally r1: = r2 * r3 + r4, setting condition codes.
S3C4530A instructio n set 3- 25 multiply long and multiply-accumulate long (mull,mlal) the instruction is only executed if the condition is true. the various conditions are defined in table 3-2. the instruction encoding is shown in figure 3-13. the multiply long instructions perform integer multiplication on two 32 bit operands and produce 64 bit results. signed and unsigned multiplication each with optional accumulate give rise to four variations. 31 27 19 15 cond 28 16 11 12 21 23 u 20 s rdhi rdlo [11:8][3:0] operand registers [19:16][15:12] source destination registers [20] set condition code 0 = do not alter condition codes 1 = set condition codes [21] accumulate 0 = multiply only 1 = multiply and accumulate [22] unsigned 0 = unsigned 1 = signed [31:28] condition field 22 0 0 0 0 1 1 0 0 1 rs rm a 8 7 4 3 0 figure 3-13. multiply long instructions the multiply forms (umull and smull) take two 32 bit numbers and multiply them to produce a 64 bit result of the form rdhi, rdlo: = rm * rs. the lower 32 bits of the 64 bit result are written to rdlo, the upper 32 bits of the result are written to rdhi. the multiply-accumulate forms (umlal and smlal) take two 32 bit numbers, multiply them and add a 64 bit number to produce a 64 bit result of the form rdhi, rdlo: = rm * rs + rdhi, rdlo. the lower 32 bits of the 64 bit number to add is read from rdlo. the upper 32 bits of the 64 bit number to add is read from rdhi. the lower 32 bits of the 64 bit result are written to rdlo. the upper 32 bits of the 64 bit result are written to rdhi. the umull and umlal instructions treat all of their operands as unsigned binary numbers and write an unsigned 64 bit result. the smull and smlal instructions treat all of their operands as two's-complement signed numbers and write a two's-complement signed 64 bit result. operand restrictions ? r15 must not be used as an operand or as a destination register. ? rdhi, rdlo, and rm must all specify different registers.
instruction set s3c 4530a 3- 26 cpsr flags setting the cpsr flags is optional, and is controlled by the s bit in the instruction. the n and z flags are set correctly on the result (n is equal to bit 63 of the result, z is set if and only if all 64 bits of the result are zero). both the c and v flags are set to meaningless values. instruction cycle times mull takes 1s + (m+1)i and mlal 1s + (m+2)i cycles to execute, where m is the number of 8 bit multiplier array cycles required to complete the multiply, which is controlled by the value of the multiplier operand specified by rs. its possible values are as follows: for signed instructions smull, smlal: ? if bits [31:8] of the multiplier operand are all zero or all one. ? if bits [31:16] of the multiplier operand are all zero or all one. ? if bits [31:24] of the multiplier operand are all zero or all one. ? in all other cases. for unsigned instructions umull, umlal: ? if bits [31:8] of the multiplier operand are all zero. ? if bits [31:16] of the multiplier operand are all zero. ? if bits [31:24] of the multiplier operand are all zero. ? in all other cases. s and i are defined as sequential (s-cycle) and internal (i-cycle), respectively.
S3C4530A instructio n set 3- 27 assembler syntax table 3-5. assembler syntax descriptions mnemonic description purpose umull{cond}{s} rdlo, rdhi, rm, rs unsigned multiply long 32 x 32 = 64 umlal{cond}{s} rdlo, rdhi, rm, rs unsigned multiply & accumulate long 32 x 32 + 64 = 64 smull{cond}{s} rdlo, rdhi, rm, rs signed multiply long 32 x 32 = 64 smlal{cond}{s} rdlo, rdhi, rm, rs signed multiply & accumulate long 32 x 32 + 64 = 64 where: { cond} two-character condition mnemonic. see table 3-2. { s} set condition codes if s present rdlo, rdhi, rm, rs expressions evaluating to a register number other than r15. examples umull r1, r4, r2, r3 ; r4, r1: = r2 * r3 umlals r1, r5, r2, r3 ; r5, r1: = r2 * r3 + r5, r1 also setting condition codes
instruction set s3c 4530a 3- 28 single data transfer (ldr, str) the instruction is only executed if the condition is true. the various conditions are defined in table 3-2. the instruction encoding is shown in figure 3-14. the single data transfer instructions are used to load or store single bytes or words of data. the memory address used in the transfer is calculated by adding an offset to or subtracting an offset from a base register. the result of this calculation may be written back into the base register if auto-indexing is required. 31 27 19 15 0 cond 28 16 11 12 21 23 b 20 l rn rd 22 01 i p u offset w 26 24 25 [15:12] source/destination registers [19:16] base register [20] load/store bit 0 = store to memory 1 = load from memory [21] write-back bit 0 = no write-back 1 = write address into base [22] byte/word bit 0 = transfer word quantity 1 = transfer byte quantity [23] up/down bit 0 = down: subtract offset from base 1 = up: add offset to base [24] pre/post indexing bit 0 = post: add offset after transfer 1 = pre: add offset bofore transfer [25] immediate offset 0 = offset is an immediate value [11:0] offset shift immediate [11:0] unsigned 12-bit immediate offset 11 11 rm [3:0] offset register [11:4] shift applied to rm [31:28] condition field 0 4 3 0 figure 3-14. single data transfer instructions
S3C4530A instructio n set 3- 29 offsets and auto-indexing the offset from the base may be either a 12 bit unsigned binary immediate value in the instruction, or a second register (possibly shifted in some way). the offset may be added to (u = 1) or subtracted from (u = 0) the base register rn. the offset modification may be performed either before (pre-indexed, p = 1) or after (post-indexed, p = 0) the base is used as the transfer address. the w bit gives optional auto increment and decrement addressing modes. the modified base value may be written back into the base (w = 1), or the old base value may be kept (w = 0). in the case of post-indexed addressing, the write back bit is redundant and is always set to zero, since the old base value can be retained by setting the offset to zero. therefore post-indexed data transfers always write back the modified base. the only use of the w bit in a post-indexed data transfer is in privileged mode code, where setting the w bit forces non- privileged mode for the transfer, allowing the operating system to generate a user address in a system where the memory management hardware makes suitable use of this hardware. shifted register offset the 8 shift control bits are described in the data processing instructions section. however, the register specified shift amounts are not available in this instruction class. see figure 3-5. bytes and words this instruction class may be used to transfer a byte (b = 1) or a word (b = 0) between an arm7tdmi register and memory. the action of ldr(b) and str(b) instructions is influenced by the bigend control signal of arm7tdmi core. the two possible configurations are described below. little-endian configuration a byte load (ldrb) expects the data on data bus inputs 7 through 0 if the supplied address is on a word boundary, on data bus inputs 15 through 8 if it is a word address plus one byte, and so on. the selected byte is placed in the bottom 8 bits of the destination register, and the remaining bits of the register are filled with zeros. please see figure 2-2. a byte store (strb) repeats the bottom 8 bits of the source register four times across data bus outputs 31 through 0. the external memory system should activate the appropriate byte subsystem to store the data. a word load (ldr) will normally use a word aligned address. however, an address offset from a word boundary will cause the data to be rotated into the register so that the addressed byte occupies bits 0 to 7. this means that half-words accessed at offsets 0 and 2 from the word boundary will be correctly loaded into bits 0 through 15 of the register. two shift operations are then required to clear or to sign extend the upper 16 bits. a word store (str) should generate a word aligned address. the word presented to the data bus is not affected if the address is not word aligned. that is, bit 31 of the register being stored always appears on data bus output 31.
instruction set s3c 4530a 3- 30 ldr from word aligned address a+3 a a+2 a+1 memory 24 16 8 0 a b c d register 24 16 8 0 a b c d ldr from address offset by 2 a+3 a a+2 a+1 memory 24 16 8 0 a b c d register 24 16 8 0 a b c d figure 3-15. little-endian offset addressing big-endian configuration a byte load (ldrb) expects the data on data bus inputs 31 through 24 if the supplied address is on a word boundary, on data bus inputs 23 through 16 if it is a word address plus one byte, and so on. the selected byte is placed in the bottom 8 bits of the destination register and the remaining bits of the register are filled with zeros. please see figure 2-1. a byte store (strb) repeats the bottom 8 bits of the source register four times across data bus outputs 31 through 0. the external memory system should activate the appropriate byte subsystem to store the data. a word load (ldr) should generate a word aligned address. an address offset of 0 or 2 from a word boundary will cause the data to be rotated into the register so that the addressed byte occupies bits 31 through 24. this means that half-words accessed at these offsets will be correctly loaded into bits 16 through 31 of the register. a shift operation is then required to move (and optionally sign extend) the data into the bottom 16 bits. an address offset of 1 or 3 from a word boundary will cause the data to be rotated into the register so that the addressed byte occupies bits 15 through 8. a word store (str) should generate a word aligned address. the word presented to the data bus is not affected if the address is not word aligned. that is, bit 31 of the register being stored always appears on data bus output 31.
S3C4530A instructio n set 3- 31 use of r15 write-back must not be specified if r15 is specified as the base register (rn). when using r15 as the base register you must remember it contains an address 8 bytes on from the address of the current instruction. r15 must not be specified as the register offset (rm). when r15 is the source register (rd) of a register store (str) instruction, the stored value will be address of the instruction plus 12. restriction on the use of base register when configured for late aborts, the following example code is difficult to unwind as the base register, rn, gets updated before the abort handler starts. sometimes it may be impossible to calculate the initial value. after an abort, the following example code is difficult to unwind as the base register, rn, gets updated before the abort handler starts. sometimes it may be impossible to calculate the initial value. example: ldr r0,[r1],r1 therefore a post-indexed ldr or str where rm is the same register as rn should not be used. data aborts a transfer to or from a legal address may cause problems for a memory management system. for instance, in a system which uses virtual memory the required data may be absent from main memory. the memory manager can signal a problem by taking the processor abort input high whereupon the data abort trap will be taken. it is up to the system software to resolve the cause of the problem, then the instruction can be restarted and the original program continued. instruction cycle times normal ldr instructions take 1s + 1n + 1i and ldr pc take 2s + 2n +1i incremental cycles, where s,n and i are defined as sequential (s-cycle), non-sequential (n-cycle), and internal (i-cycle), respectively. str instructions take 2n incremental cycles to execute.
instruction set s3c 4530a 3- 32 assembler syntax {cond}{b}{t} rd,

where: ldr load from memory into a register str store from a register into memory { cond} two-character condition mnemonic. see table 3-2. { b} if b is present then byte transfer, otherwise word transfer { t} if t is present the w bit will be set in a post-indexed instruction, forcing non- privileged mode for the transfer cycle. t is not allowed when a pre-indexed addressing mode is specified or implied. rd an expression evaluating to a valid register number. rn and rm expressions evaluating to a register number. if rn is r15 then the assembler will subtract 8 from the offset value to allow for arm7tdmi pipelining. in this case base write-back should not be specified.

ldr load from memory into a register str store from a register into memory { cond} two-character condition mnemonic. see table 3-2. h transfer half-word quantity sb load sign extended byte (only valid for ldr) sh load sign extended half-word (only valid for ldr) rd an expression evaluating to a valid register number.

ldc load from memory to coprocessor stc store from coprocessor to memory { l} when present perform long transfer (n = 1), otherwise perform short transfer (n = 0) { cond} two character condition mnemonic. see table 3-2. p# the unique number of the required coprocessor cd an expression evaluating to a valid coprocessor register number that is placed in the crd field

can be: 1 an expression which generates an address: the assembler will attempt to generate an instruction using the pc as a base and a corrected immediate offset to address the location given by evaluating the expression. this will be a pc relative, pre-indexed address. if the address is out of range, an error will be generated 2 a pre-indexed addressing specification: [rn] offset of zero [rn,<#expression>]{!} offset of bytes a post-indexed addressing specification: rn],<#expression offset of bytes {!} write back the base register (set the w bit) if! is present rn is an expression evaluating to a valid arm7tdmi register number. note if rn is r15, the assembler will subtract 8 from the offset value to allow for arm7tdmi pipelining. examples ldc p1,c2,table ; load c2 of coproc 1 from address ; table, using a pc relative address. stceql p2,c3,[r5,#24]! ; conditionally store c3 of coproc 2 ; into an address 24 bytes up f rom r5, ; write this address back to r5, and use ; long transfer option (probably to store multiple words). note although the address offset is expressed in bytes, the instruction offset field is in words. the assembler will adjust the offset appropriately.
instruction set s3c 4530a 3- 56 coprocessor register transfers (mrc, mcr) the instruction is only executed if the condition is true. the various conditions are defined in table 3-2.. the instruction encoding is shown in figure 3-27 . this class of instruction is used to communicate information directly between arm7tdmi and a coprocessor. an example of a coprocessor to arm7tdmi register transfer (mrc) instruction would be a fix of a floating point value held in a coprocessor, where the floating point number is converted into a 32 bit integer within the coprocessor, and the result is then transferred to arm7tdmi register. a float of a 32 bit value in arm7tdmi register into a floating point value within the coprocessor illustrates the use of arm7tdmi register to coprocessor transfer (mcr). an important use of this instruction is to communicate control information directly from the coprocessor into the arm7tdmi cpsr flags. as an example, the result of a comparison of two floating point values within a coprocessor can be moved to the cpsr to control the subsequent flow of execution. 31 27 19 15 cond 28 16 11 12 21 23 20 l crn rd [3:0] coprocessor operand register [7:5] coprocessor information [11:8] coprocessor number [15:12] arm source/destination register [19:16] coprocessor source/destination register [20] load/store bit 0 = store to coprocessor 1 = load from coprocessor [21] coprocessor operation mode [31:28] condition field 1110 cp opc cp# 24 crm 1 cp 8 7 5 4 3 0 figure 3-27. coprocessor register transfer instructions the coprocessor fields the cp# field is used, as for all coprocessor instructions, to specify which coprocessor is being called upon. the cp opc, crn, cp and crm fields are used only by the coprocessor, and the interpretation presented here is derived from convention only. other interpretations are allowed where the coprocessor functionality is incompatible with this one. the conventional interpretation is that the cp opc and cp fields specify the operation the coprocessor is required to perform, crn is the coprocessor register which is the source or destination of the transferred information, and crm is a second coprocessor register which may be involved in some way which depends on the particular operation specified.
S3C4530A instructio n set 3- 57 transfers to r15 when a coprocessor register transfer to arm7tdmi has r15 as the destination, bits 31, 30, 29 and 28 of the transferred word are copied into the n, z, c and v flags respectively. the other bits of the transferred word are ignored, and the pc and other cpsr bits are unaffected by the transfer. transfers from r15 a coprocessor register transfer from arm7tdmi with r15 as the source register will store the pc+ 12. instruction cycle times mrc instructions take 1s + (b+1)i +1c incremental cycles to execute, where s, i and c are defined as sequential (s-cycle), internal (i-cycle), and coprocessor register transfer (c-cycle), respectively. mcr instructions take 1s + bi +1c incremental cycles to execute, where b is the number of cycles spent in the coprocessor busy-wait loop. assembler syntax {cond} p#,,rd,cn,cm{,} mrc move from coprocessor to arm7tdmi register (l = 1) mcr move from arm7tdmi register to coprocessor (l = 0) { cond} two character condition mnemonic. see table 3-2. p# the unique number of the required coprocessor evaluated to a constant and placed in the cp opc field rd an expression evaluating to a valid arm7tdmi register number cn and cm expressions evaluating to the valid coprocessor register numbers crn and crm respectively where present is evaluated to a constant and placed in the cp field examples mrc p2,5,r3,c5,c6 ; request coproc 2 to perform operation 5 ; on c5 and c6, and transfer the (single ; 32-bit word) result back to r3. mcr p6,0,r4,c5,c6 ; request coproc 6 to perform operation 0 ; on r4 and place the result in c6. mrceq p3,9,r3,c5,c6,2 ; conditionally request coproc 3 to ; perform operation 9 (type 2) on c5 and ; c6, and transfer the result back to r3.
instruction set s3c 4530a 3- 58 undefined instruction the instruction is only executed if the condition is true. the various conditions are defined in table 3-2. the instruction format is shown in figure 3-28. 31 27 cond 28 25 24 011 xxxxxxxxxxxxxxxxxxxx 1 xxxx 5 4 3 0 figure 3-28. undefined instruction if the condition is true, the undefined instruction trap will be taken. note that the undefined instruction mechanism involves offering this instruction to any coprocessors which may be present, and all coprocessors must refuse to accept it by driving cpa and cpb high. instruction cycle times this instruction takes 2s + 1i + 1n cycles, where s, n and i are defined as sequential (s-cycle), non-sequential (n-cycle), and internal (i-cycle). assembler syntax the assembler has no mnemonics for generating this instruction. if it is adopted in the future for some specified use, suitable mnemonics will be added to the assembler. until such time, this instruction must not be used.
S3C4530A instructio n set 3- 59 instruction set examples the following examples show ways in which the basic arm7tdmi instructions can combine to give efficient code. none of these methods saves a great deal of execution time (although they may save some), mostly they just save code. using the conditional instructions using conditionals for logical or cmp rn,#p ; if rn=p or rm=q then goto label. beq label cmp rm,#q beq label this can be replaced by cmp rn,#p cmpne rm,#q ; if condition not satisfied try other test. beq label absolute value teq rn,#0 ; test sign rsbmi rn,rn,#0 ; and 2's complement if necessary. multiplication by 4, 5 or 6 (run time) mov rc,ra,lsl#2 ; multiply by 4, cmp rb,#5 ; test value, addcs rc,rc,ra ; complete multiply by 5, addhi rc,rc,ra ; complete multiply by 6. combining discrete and range tests teq rc,#127 ; discrete test, cmpne rc,# ? ?-1 ; range test movls rc,# ?? ; if rc<= ?? or rc=ascii(127) ; then rc:= ? ?
instruction set s3c 4530a 3- 60 division and remainder a number of divide routines for specific applications are provided in source form as part of the ansi c library provided with the arm cross development toolkit, available from your supplier. a short general purpose divide routine follows. ; enter with numbers in ra and rb. mov rcnt,#1 ; bit to control the division. div1 cmp rb,#0x80000000 ; move rb until greater than ra. cmpcc rb,ra movcc rb,rb,asl#1 movcc rcnt,rcnt,asl#1 bcc div1 mov rc,#0 div2 cmp ra,rb ; test for possible subtraction. subcs ra,ra,rb ; subtract if ok, addcs rc,rc,rcnt ; put relevant bit into result movs rcnt,rcnt,lsr#1 ; shift control bit movne rb,rb,lsr#1 ; halve unless finished. bne div2 ; divide result in rc, remainder in ra. overflow detection in the arm7tdmi 1. overflow in unsigned multiply with a 32-bit result umull rd,rt,rm,rn ; 3 to 6 cycles teq rt,#0 ; +1 cycle and a register bne overflow 2. overflow in signed multiply with a 32-bit result smull rd,rt,rm,rn ; 3 to 6 cycles teq rt,rd asr#31 ; +1 cycle and a register bne overflow 3. overflow in unsigned multiply accumulate with a 32 bit result umlal rd,rt,rm,rn ; 4 to 7 cycles teq rt,#0 ; +1 cycle and a register bne overflow 4. overflow in signed multiply accumulate with a 32 bit result smlal rd,rt,rm,rn ; 4 to 7 cycles teq rt,rd, asr#31 ; +1 cycle a nd a register bne overflow
S3C4530A instructio n set 3- 61 5. overflow in unsigned multiply accumulate with a 64 bit result umull rl,rh,rm,rn ; 3 to 6 cycles adds rl,rl,ra1 ; lower accumulate adc rh,rh,ra2 ; upper accumulate bcs overflow ; 1 cycle and 2 registers 6. overflow in signed multiply accumulate with a 64 bit result smull rl,rh,rm,rn ; 3 to 6 cycles adds rl,rl,ra1 ; lower accumulate adc rh,rh,ra2 ; upper accumulate bvs overflow ; 1 cycle and 2 registers note overflow checking is not applicable to unsigned and signed multiplies with a 64-bit result, since overflow does not occur in such calculations. pseudo-random binary sequence generator it is often necessary to generate (pseudo-) random numbers and the most efficient algorithms are based on shift generators with exclusive-or feedback rather like a cyclic redundancy check generator. unfortunately the sequence of a 32 bit generator needs more than one feedback tap to be maximal length (i.e. 2^32-1 cycles before repetition), so this example uses a 33 bit register with taps at bits 33 and 20. the basic algorithm is newbit: = bit 33 eor bit 20, shift left the 33 bit number and put in newbit at the bottom; this operation is performed for all the newbits needed (i.e. 32 bits). the entire operation can be done in 5 s cycles: ; enter with seed in ra (32 bits), ; rb (1 bit in rb lsb), uses rc. tst rb,rb,lsr#1 ; top bit into carry movs rc,ra,rrx ; 33 bit rotate right adc rb,rb,rb ; carry into lsb of rb eor rc,rc,ra,lsl#12 ; (involved!) eor ra,rc,rc,lsr#20 ; (similarly involved!) new seed in ra, rb as before multiplication by constant using the barrel shifter multiplication by 2^n (1,2,4,8,16,32..) mov ra, rb, lsl #n multiplication by 2^n+1 (3,5,9,17..) add ra,ra,ra,lsl #n multiplication by 2^n-1 (3,7,15..) rsb ra,ra,ra,lsl #n
instruction set s3c 4530a 3- 62 multiplication by 6 add ra,ra,ra,lsl #1 ; multiply by 3 mov ra,ra,lsl#1 ; and then by 2 multiply by 10 and add in extra number add ra,ra,ra,lsl#2 ; multiply by 5 add ra,rc,ra,lsl#1 ; multiply by 2 and add in next digit general recursive method for rb := ra*c, c a constant: 1. if c even, say c = 2^n*d, d odd: d=1: mov rb,ra,lsl #n d<>1: {rb := ra*d} mov rb,rb,lsl #n 2. if c mod 4 = 1, say c = 2^n*d+1, d odd, n>1: d=1: add rb,ra,ra,lsl #n d<>1: {rb := ra*d} add rb,ra,rb,lsl #n 3. if c mod 4 = 3, say c = 2^n*d-1, d odd, n>1: d=1: rsb rb,ra,ra,lsl #n d<>1: {rb := ra*d} rsb rb,ra,rb,lsl #n this is not quite optimal, but close. an example of its non-optimality is multiply by 45 which is done by: rsb rb,ra,ra,lsl# 2 ; multiply by 3 rsb rb,ra,rb,lsl#2 ; multiply by 4*3-1 = 11 add rb,ra,rb,lsl# 2 ; multiply by 4*11+1 = 45 rather than by: add rb,ra,ra,lsl#3 ; multiply by 9 add rb,rb,rb,lsl#2 ; multiply by 5*9 = 45
S3C4530A instructio n set 3- 63 loading a word from an unknown alignment ; enter with address in ra (32 bits) uses ; rb, rc result in rd. note d must be less than c e.g. 0,1 bic rb,ra,#3 ; get word aligned address ldmia rb,{rd,rc} ; get 64 bits containing answer and rb,ra,#3 ; correction factor in bytes movs rb,rb,ls l#3 ; ...now in bits and test if aligned movne rd,rd,lsr rb ; produce bottom of result word (if not aligned) rsbne rb,rb,#32 ; get other shift amount orrne rd,rd,rc,lsl rb ; combine two halves to get result
instruction set s3c 4530a 3- 64 thumb instruction set format the thumb instruction sets are 16-bit versions of arm instruction sets (32-bit format). the arm instructions are reduced to 16-bit versions, thumb instructions, at the cost of versatile functions of the arm instruction sets. the thumb instructions are decompressed to the arm instructions by the thumb decompressor inside the arm7tdmi core. as the thumb instructions are compressed arm instructions, the thumb instructions have the 16-bit format instructions and have some restrictions. the restrictions by 16-bit format is fully notified for using the thumb instructions. format summary the thumb instruction set formats are shown in the following figure. move shifted register 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 0 l 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 0 0 l 1 0 r 1 1 0 1 0 sp 1 l l s h 0 0 1 b l 0 1 h 0 1 b 0 0 1 1 1 i op op op op op l 0 s 1 offset5 rs rd rn/offset3 rd rs rd offset8 rs rd/hd rd h1 h2 rs/hs rd word8 rd rb ro ro rb rd offset5 rb rd rb rd offset5 rd rd word8 word8 sword7 rb cond rlist rlist softset8 value8 offset11 offset add/subtract move/compare/add/ subtract immediate alu operations hi regiter operations /branch exchange pc-relative load load/store with register offset load/store with immediate offset load/store sign-extended byte/halfword load/store halfword sp-relative load/store load address add offset to stack pointer push/pop register multiple load/store conditional branch software interrupt unconditional branch long branch with link 15 14 13 12 11 10 9 8 7 6 5 4 2 3 1 0 15 14 13 12 11 10 9 8 7 6 5 4 2 3 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 figure 3-29. thumb instruction set formats
S3C4530A instructio n set 3- 65 opcode summary the following table summarises the thumb instruction set. for further information about a particular instruction please refer to the sections listed in the right-most column. table 3-7. thumb instruction set opcodes mnemonic instruction lo-register operand hi-register operand condition codes set adc add with carry v ? v add add v v v (1) and and v ? v asr arithmetic shift right v ? v b unconditional branch v ? ? bxx conditional branch v ? ? bic bit clear v ? v bl branch and link v ? ? bx branch and exchange v v ? cmn compare negative v ? v cmp compare v v v eor eor v ? v ldmia load multiple v ? ? ldr load word v ? ? ldrb load byte v ? ? ldrh load half-word v ? ? lsl logical shift left v ? v ldsb load sign-extended byte v ? ? ldsh load sign-extended half-word v ? ? lsr logical shift right v ? v mov move register v v v (2) mul multiply v ? v mvn move negative register v ? v neg negate v ? v orr or v ? v pop pop registers v ? ? push push registers v ? ? por rotate right v ? v
instruction set s3c 4530a 3- 66 table 3-7. thumb instruction set opcodes (continued) mnemonic instruction lo-register operand hi-register operand condition codes set sbc subtract with carry v ? v stmia store multiple v ? ? str store word v ? ? strb store byte v ? ? strh store half-word v ? ? swi software interrupt ? ? ? sub subtract v ? v tst test bits v ? v notes: 1. the condition codes are unaffected by the format 5, 12 and 13 versions of this instruction. 2. the condition codes are unaffected by the format 5 version of this instruction.
S3C4530A instructio n set 3- 67 format 1: move shifted register 15 0 0 14 10 [2:0] destination register [5:3] source register [10:6] immediate vale [12:11] opcode 0 = lsl 1 = lsr 2 = asr offset5 6 5 3 2 rd 0 0 13 12 11 op rs figure 3-30. format 1 operation these instructions move a shifted value between lo registers. the thumb assembler syntax is shown in table 3-8. note all instructions in this group set the cpsr condition codes. table 3-8. summary of format 1 instructions op thumb assembler arm equivalent action 00 lsl rd, rs, #offset5 movs rd, rs, lsl #offset5 shift rs left by a 5-bit immediate value and store the result in rd. 01 lsr rd, rs, #offset5 movs rd, rs, lsr #offset5 perform logical shift right on rs by a 5-bit immediate value and store the result in rd. 10 asr rd, rs, #offset5 movs rd, rs, asr #offset5 perform arithmetic shift right on rs by a 5-bit immediate value and store the result in rd. instruction cycle times all instructions in this format have an equivalent arm instruction as shown in table 3-8. the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. examples lsr r2, r5, #27 ; logical shift right the contents ; of r5 by 27 and store the result in r2. ; set condition codes on the result.
instruction set s3c 4530a 3- 68 format 2: add/subtract 15 0 14 10 [2:0] destination register [5:3] source register [8:6] register/immediate value [9] opcode 0 = add 1 = sub [10] immediate flag 0 = register operand 1 = immediate oerand rn/offset3 rd 0 0 13 12 11 op rs 9 8 1 1 1 6 5 3 2 0 figure 3-31. format 2 operation these instructions allow the contents of a lo register or a 3-bit immediate value to be added to or subtracted from a lo register. the thumb assembler syntax is shown in table 3-9. note all instructions in this group set the cpsr condition codes. table 3-9. summary of format 2 instructions op i thumb assembler arm equivalent action 0 0 add rd, rs, rn adds rd, rs, rn add contents of rn to contents of rs. place result in rd. 0 1 add rd, rs, #offset3 adds rd, rs, #offset3 add 3-bit immediate value to contents of rs. place result in rd. 1 0 sub rd, rs, rn subs rd, rs, rn subtract contents of rn from contents of rs. place result in rd. 1 1 sub rd, rs, #offset3 subs rd, rs, #offset3 subtract 3-bit immediate value from contents of rs. place result in rd.
S3C4530A instructio n set 3- 69 instruction cycle times all instructions in this format have an equivalent arm instruction as shown in table 3-9. the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. examples add r0, r3, r4 ; r0 : = r3 + r4 and set condition codes on the result. sub r6, r2, #6 ; r6 : = r2 - 6 and set condition codes.
instruction set s3c 4530a 3- 70 format 3: move/compare/add/subtract immediate 15 0 0 14 10 [7:0] immediate value [10:8] source/destination register [12:11] opcode 0 = mov 1 = cmp 2 = add 3 = sub offset8 rd 0 0 13 12 11 op 7 8 figure 3-32. format 3 operations the instructions in this group perform operations between a lo register and an 8-bit immediate value. the thumb assembler syntax is shown in table 3-10. note all instructions in this group set the cpsr condition codes. table 3-10. summary of format 3 instructions op thumb assembler arm equivalent action 00 mov rd, #offset8 movs rd, #offset8 move 8-bit immediate value into rd. 01 cmp rd, #offset8 cmp rd, #offset8 compare contents of rd with 8-bit immediate value. 10 add rd, #offset8 adds rd, rd, #offset8 add 8-bit immediate value to contents of rd and place the result in rd. 11 sub rd, #offset8 subs rd, rd, #offset8 subtract 8-bit immediate value from contents of rd and place the result in rd. instruction cycle times all instructions in this format have an equivalent arm instruction as shown in table 3-10. the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. examples mov r0, #128 ; r0 : = 128 and set condition codes cmp r2, #62 ; set condition codes on r2 - 62 add r1, #255 ; r1 : = r1 + 255 and set condition codes sub r6, #145 ; r6 : = r6 - 145 and set condition codes
S3C4530A instructio n set 3- 71 format 4: alu operations 15 0 0 14 10 [2:0] source/destination register [5:3] source register 2 [9:6] opcode 5 6 3 rd 0 0 13 12 11 op rs 0 0 0 9 2 figure 3-33. format 4 operation the following instructions perform alu operations on a lo register pair. note all instructions in this group set the cpsr condition codes table 3-11. summary of format 4 instructions op thumb assembler arm equivalent action 0000 and rd, rs ands rd, rd, rs rd: = rd and rs 0001 eor rd, rs eors rd, rd, rs rd: = rd eor rs 0010 lsl rd, rs movs rd, rd, lsl rs rd : = rd << rs 0011 lsr rd, rs movs rd, rd, lsr rs rd : = rd >> rs 0100 asr rd, rs movs rd, rd, asr rs rd : = rd asr rs 0101 adc rd, rs adcs rd, rd, rs rd : = rd + rs + c-bit 0110 sbc rd, rs sbcs rd, rd, rs rd : = rd - rs - not c-bit 0111 ror rd, rs movs rd, rd, ror rs rd : = rd ror rs 1000 tst rd, rs tst rd, rs set condition codes on rd and rs 1001 neg rd, rs rsbs rd, rs, #0 rd = - rs 1010 cmp rd, rs cmp rd, rs set condition codes on rd - rs 1011 cmn rd, rs cmn rd, rs set condition codes on rd + rs 1100 orr rd, rs orrs rd, rd, rs rd: = rd or rs 1101 mul rd, rs muls rd, rs, rd rd: = rs * rd 1110 bic rd, rs bics rd, rd, rs rd: = rd and not rs 1111 mvn rd, rs mvns rd, rs rd: = not rs
instruction set s3c 4530a 3- 72 instruction cycle times all instructions in this format have an equivalent arm instruction as shown in table 3-11. the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. examples eor r3, r4 ; r3 : = r3 eor r4 and set condition codes ror r1, r0 ; rotate right r1 by the value in r0, store ; the result in r1 and set condition codes neg r5, r3 ; subtract the contents of r3 from zero, ; store the result in r5. set condition codes ie r5 = - r3 cmp r2, r6 ; set the condition codes on the result of r2 - r6 mul r0, r7 ; r0 : = r7 * r0 and set condition codes
S3C4530A instructio n set 3- 73 format 5: hi-register operations/branch exchange 15 0 0 14 10 [2:0] destination register [5:3] source register [6] hi operand flag 2 [7] hi operand flag 1 [9:8] opcode 6 5 3 2 rd/hd 0 0 13 12 11 op rs/hs 0 0 0 9 8 7 h1 h2 figure 3-34. format 5 operation there are four sets of instructions in this group. the first three allow add, cmp and mov operations to be performed between lo and hi registers, or a pair of hi registers. the fourth, bx, allows a branch to be performed which may also be used to switch processor state. the thumb assembler syntax is shown in table 3-12. note in this group only cmp (op = 01) sets the cpsr condition codes. the action of h1 = 0, h2 = 0 for op = 00 (add), op = 01 (cmp) and op = 10 (mov) is undefined, and should not be used.
instruction set s3c 4530a 3- 74 table 3-12. summary of format 5 instructions op h1 h2 thumb assembler arm equivalent action 00 0 1 add rd, hs add rd, rd, hs add a register in the range 8-15 to a register in the range 0-7. 00 1 0 add hd, rs add hd, hd, rs add a register in the range 0-7 to a register in the range 8-15. 00 1 1 add hd, hs add hd, hd, hs add two registers in the range 8-15. 01 0 1 cmp rd, hs cmp rd, hs compare a register in the range 0-7 with a register in the range 8-15. set the condition code flags on the result. 01 1 0 cmp hd, rs cmp hd, rs compare a register in the range 8-15 with a register in the range 0-7. set the condition code flags on the result. 01 1 1 cmp hd, hs cmp hd, hs compare two registers in the range 8-15. set the condition code flags on the result. 10 0 1 mov rd, hs mov rd, hs move a value from a register in the range 8-15 to a register in the range 0-7. 10 1 0 mov hd, rs mov hd, rs move a value from a register in the range 0-7 to a register in the range 8-15. 00 0 1 mov hd, hs mov hd, hs move a value between two registers in the range 8-15. 00 1 0 bx rs bx rs perform branch (plus optional state change) to address in a register in the range 0-7. 00 1 1 bx hs bx hs perform branch (plus optional state change) to address in a register in the range 8-15. instruction cycle times all instructions in this format have an equivalent arm instruction as shown in table 3-12. the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. the bx instruction bx performs a branch to a routine whose start address is specified in a lo or hi register. bit 0 of the address determines the processor state on entry to the routine: bit 0 = 0 causes the processor to enter arm state. bit 0 = 1 causes the processor to enter thu mb state. note the action of h1 = 1 for this instruction is undefined, and should not be used.
S3C4530A instructio n set 3- 75 examples hi- register operations add pc, r5 ; pc := pc + r5 but don't set the condition codes.cmp r4, r12 ; set the condition codes on the result of r4 - r12. mov r15, r14 ; move r14 (lr) into r15 (pc) ; but don't set the condition codes, ; eg. return from subroutine. branch and exchange ; switch from thumb to arm sta te. adr r1,outofthumb ; load address of outofthumb into r1. mov r11,r1 bx r11 ; transfer the contents of r11 into the pc. ; bit 0 of r11 determines whether ; arm or thumb state is entered, ie. arm state here. ... align code32 outofthumb ; now processing arm instructions... using r15 as an operand if r15 is used as an operand, the value will be the address of the instruction + 4 with bit 0 cleared. executing a bx pc in thumb state from a non-word aligned address will result in unpredictable execution.
instruction set s3c 4530a 3- 76 format 6: pc-relative load 15 0 0 14 10 [7:0] immediate value [10:8] destination register word 8 0 0 13 12 11 rd 0 0 8 7 figure 3-35. format 6 operation this instruction loads a word from an address specified as a 10-bit immediate offset from the pc. the thumb assembler syntax is shown below. table 3-13. summary of pc-relative load instruction thumb assembler arm equivalent action ldr rd, [pc, #imm] ldr rd, [r15, #imm] add unsigned offset (255 words, 1020 bytes) in imm to the current value of the pc. load the word from the resulting address into rd. note: the value specified by #imm is a full 10-bit address, but must always be word-aligned (ie with bits 1:0 set to 0), since the assembler places #imm >> 2 in field word 8. the value of the pc will be 4 bytes greater than the address of this instruction, but bit 1 of the pc is forced to 0 to ensure it is word aligned. instruction cycle times all instructions in this format have an equivalent arm instruction. the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. examples ldr r3,[pc,#844] ; load into r3 the word found at the ; address formed by adding 844 to pc. ; bit[1] of pc is forced to zero. ; note that the thumb opcode will contain ; 211 as the word8 value.
S3C4530A instructio n set 3- 77 format 7: load/store with register offset [2:0] source/destination register [5:3] base register [8:6] offset register [10] byte/word flag 0 = transfer word quantity 1 = transfer byte quantity [11] load/store flag 0 = store to memory 1 = load from memory 15 0 0 14 10 6 5 3 2 rd 1 0 13 12 11 rb 1 l b 9 8 ro 0 figure 3-36. format 7 operation these instructions transfer byte or word values between registers and memory. memory addresses are pre- indexed using an offset register in the range 0-7. the thumb assembler syntax is shown in table 3-14. table 3-14. summary of format 7 instructions l b thumb assembler arm equivalent action 0 0 str rd, [rb, ro] str rd, [rb, ro] pre-indexed word store: calculate the target address by adding together the value in rb and the value in ro. store the contents of rd at the address. 0 1 strb rd, [rb, ro] strb rd, [rb, ro] pre-indexed byte store: calculate the target address by adding together the value in rb and the value in ro. store the byte value in rd at the resulting address. 1 0 ldr rd, [rb, ro] ldr rd, [rb, ro] pre-indexed word load: calculate the source address by adding together the value in rb and the value in ro. load the contents of the address into rd. 1 1 ldrb rd, [rb, ro] ldrb rd, [rb, ro] pre-indexed byte load: calculate the source address by adding together the value in rb and the value in ro. load the byte value at the resulting address.
instruction set s3c 4530a 3- 78 instruction cycle times all instructions in this format have an equivalent arm instruction as shown in table 3-14. the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. examples str r3, [r2,r6] ; store word in r3 at the address ; formed by adding r6 to r2. ldrb r2, [r0,r7] ; load into r2 the byte found at ; the address formed by adding r7 to r0.
S3C4530A instructio n set 3- 79 format 8: load/store sign-extended byte/half-word [2:0] destination register [5:3] base register [8:6] offset register [10] sign-extended flag 0 = operand not sing-extended 1 = operand sing-extended [11] h flag 15 0 0 14 10 6 5 3 2 rd 1 0 13 12 11 rb 1 h s 9 8 ro 1 figure 3-37. format 8 operation these instructions load optionally sign-extended bytes or half-words, and store half-words. the thumb assembler syntax is shown below. table 3-15. summary of format 8 instructions l b thumb assembler arm equivalent action 0 0 strh rd, [rb, ro] strh rd, [rb, ro] store half-word: add ro to base address in rb. store bits 0?15 of rd at the resulting address. 0 1 ldrh rd, [rb, ro] ldrh rd, [rb, ro] load half-word: add ro to base address in rb. load bits 0?15 of rd from the resulting address, and set bits 16-31 of rd to 0. 1 0 ldsb rd, [rb, ro] ldrsb rd, [rb, ro] load sign-extended byte: add ro to base address in rb. load bits 0?7 of rd from the resulting address, and set bits 8-31 of rd to bit 7. 1 1 ldsh rd, [rb, ro] ldrsh rd, [rb, ro] load sign-extended half-word: add ro to base address in rb. load bits 0?15 of rd from the resulting address, and set bits 16-31 of rd to bit 15.
instruction set s3c 4530a 3- 80 instruction cycle times all instructions in this format have an equivalent arm instruction as shown in table 3-15. the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. examples strh r4, [r3, r0] ; store the lower 16 bits of r4 at the ; address formed by adding r0 to r3. ldsb r2, [r7, r1] ; load into r2 the sign extended byte ; found at the address formed by adding r1 to r7. ldsh r3, [r4, r2] ; load into r3 the sign extended half-word ; found at the address formed by adding r2 to r4.
S3C4530A instructio n set 3- 81 format 9: load/store with immediate offset [2:0] source/destination register [5:3] base register [10:6] offset register [11] load/store flag 0 = store to memory 1 = load from memory [12] byte/word flad 0 = transfer word quantity 1 = transfer byte quantity 15 0 0 14 10 6 5 3 2 rd 1 1 13 12 11 rb b l offset5 figure 3-38. format 9 operation these instructions transfer byte or word values between registers and memory using an immediate 5 or 7-bit offset. the thumb assembler syntax is shown in table 3-16 table 3-16. summary of format 9 instructions l b thumb assembler arm equivalent action 0 0 str rd, [rb, #imm] str rd, [rb, #imm] calculate the target address by adding together the value in rb and imm. store the contents of rd at the address. 0 1 ldr rd, [rb, #imm] ldr rd, [rb, #imm] calculate the source address by adding together the value in rb and imm. load rd from the address. 1 0 strb rd, [rb, #imm] strb rd, [rb, #imm] calculate the target address by adding together the value in rb and imm. store the byte value in rd at the address. 1 1 ldrb rd, [rb, #imm] ldrb rd, [rb, #imm] calculate source address by adding together the value in rb and imm. load the byte value at the address into rd. note: for word accesses (b = 0), the value specified by #imm is a full 7-bit address, but must be word-aligned (ie with bits 1:0 set to 0), since the assembler places #imm >> 2 in the offset5 field.
instruction set s3c 4530a 3- 82 instruction cycle times all instructions in this format have an equivalent arm instruction as shown in table 3-16. the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. examples ldr r2, [r5,#116] ; load into r2 the word found at the ; address formed by adding 116 to r5. ; note that the thumb opcode will ; contain 29 as the offset5 value. strb r1, [r0,#13] ; store the lower 8 bits of r1 at the ; address formed by adding 13 to r0. ; note that the thumb opcode will ; contain 13 as the offset5 value.
S3C4530A instructio n set 3- 83 format 10: load/store half-word [2:0] source/destination register [5:3] base register [10:6] immediate value [11] load/store flag 0 = store to memory 1 = load from memory 15 0 0 14 10 6 5 3 2 rd 1 0 13 12 11 rb 0 l offset5 figure 3-39. format 10 operation these instructions transfer half-word values between a lo register and memory. addresses are pre-indexed, using a 6-bit immediate value. the thumb assembler syntax is shown in table 3-17. table 3-17. half-word data transfer instructions l thumb assembler arm equivalent action 0 strh rd, [rb, #imm] strh rd, [rb, #imm] add #imm to base address in rb and store bits 0?15 of rd at the resulting address. 1 ldrh rd, [rb, #imm] ldrh rd, [rb, #imm] add #imm to base address in rb. load bits 0?15 from the resulting address into rd and set bits 16-31 to zero. note: #imm is a full 6-bit address but must be half-word-aligned (ie with bit 0 set to 0), since the assembler places #imm >> 1 in the offset5 field. instruction cycle times all instructions in this format have an equivalent arm instruction as shown in table 3-17. the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. examples strh r6, [r1, #56] ; store the lower 16 bits of r4 at the address formed by ; adding 56 r1. note that the thumb opcode will contain ; 28 as the offset5 value. ldrh r4, [r7, #4] ; load into r4 the half-word found at the address formed by ; adding 4 to r7. note that the thumb opcode will ; contain 2 as the offset5 value.
instruction set s3c 4530a 3- 84 format 11: sp-relative load/store [7:0] immediate value [10:8] destination register [11] load/store bit 0 = store to memory 1 = load from memory 15 0 1 14 10 0 0 13 12 11 word 8 1 l rd 7 8 figure 3-40. format 11 operation the instructions in this group perform an sp-relative load or store. the thumb assembler syntax is shown in the following table. table 3-18. sp-relative load/store instructions l thumb assembler arm equivalent action 0 str rd, [sp, #imm] str rd, [r13 #imm] add unsigned offset (255 words, 1020 bytes) in imm to the current value of the sp (r7). store the contents of rd at the resulting address. 1 ldr rd, [sp, #imm] ldr rd, [r13 #imm] add unsigned offset (255 words, 1020 bytes) in imm to the current value of the sp (r7). load the word from the resulting address into rd. note: the offset supplied in #imm is a full 10-bit address, but must always be word-aligned (ie bits 1:0 set to 0), since the assembler places #imm >> 2 in the word8 field. instruction cycle times all instructions in this format have an equivalent arm instruction as shown in table 3-18. the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. examples str r4, [sp,#492] ; store the contents of r4 at the address ; formed by adding 492 to sp (r13). ; note that the thumb opcode will contain ; 123 as the word8 value.
S3C4530A instructio n set 3- 85 format 12: load addres [7:0] 8-bit unsigned constant [10:8] destination register [11] source 0 = pc 1 = sp 15 0 1 14 10 0 1 13 12 11 word 8 0 sp rd 7 8 figure 3-41. format 12 operation these instructions calculate an address by adding an 10-bit constant to either the pc or the sp, and load the resulting address into a register. the thumb assembler syntax is shown in the following table. table 3-19. load address sp thumb assembler arm equivalent action 0 add rd, pc, #imm add rd, r15, #imm add #imm to the current value of the program counter (pc) and load the result into rd. 1 add rd, sp, #imm add rd, r13, #imm add #imm to the current value of the stack pointer (sp) and load the result into rd. note: the value specified by #imm is a full 10-bit value, but this must be word-aligned (ie with bits 1:0 set to 0) since the assembler places #imm >> 2 in field word 8. where the pc is used as the source register (sp = 0), bit 1 of the pc is always read as 0. the value of the pc will be 4 bytes greater than the address of the instruction before bit 1 is forced to 0. the cpsr condition codes are unaffected by these instructions.
instruction set s3c 4530a 3- 86 instruction cycle times all instructions in this format have an equivalent arm instruction as shown in table 3-19. the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. examples add r2, pc, #572 ; r2: = pc + 572, but don't set the ; condition codes. bit[1] of pc is forced to zero. ; note that the thumb opcode will ; contain 143 as the word8 value. add r6, sp, #212 ; r6: = sp (r13) + 212, but don't ; set the condition codes. ; note that the thumb opcode will ; contain 53 as the word 8 value.
S3C4530A instructio n set 3- 87 format 13: add offset to stack pointer [6:0] 7-bit immediate value [7] sign flag 0 = offset is positive 1 = offset is negative 15 0 1 14 10 0 1 13 12 11 sword 7 1 0 0 7 8 9 6 0 0 s figure 3-42. format 13 operation this instruction adds a 9-bit signed constant to the stack pointer. the following table shows the thumb assembler syntax. table 3-20. the add sp instruction s thumb assembler arm equivalent action 0 add sp, #imm add r13, r13, #imm add #imm to the stack pointer (sp). 1 add sp, #-imm sub r13, r13, #imm add #-imm to the stack pointer (sp). note: the offset specified by #imm can be up to -/+ 508, but must be word-aligned (ie with bits 1:0 set to 0) since the assembler converts #imm to an 8-bit sign + magnitude number before placing it in field sword7. the condition codes are not set by this instruction. instruction cycle times all instructions in this format have an equivalent arm instruction as shown in table 3-20. the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. examples add sp, #268 ; sp (r13): = sp + 268, but don't set the condi tion codes. ; note that the thumb opcode will ; contain 67 as the word7 value and s = 0. add sp, #-104 ; sp (r13): = sp - 104, but don't set the condition codes. ; note that the thumb opcode will contain ; 26 as the word7 value and s = 1.
instruction set s3c 4530a 3- 88 format 14: push/pop registers [7:0] register list [8] pc/lr bit 0 = do not store lr/load pc 1 = store lr/load pc [11] load/store bit 0 = store to memory 1 = load from memory 15 0 1 14 10 0 1 13 12 11 rlist 1 l 0 7 8 9 1 r figure 3-43. format 14 operation the instructions in this group allow registers 0-7 and optionally lr to be pushed onto the stack, and registers 0-7 and optionally pc to be popped off the stack. the thumb assembler syntax is shown in table 3-21. note the stack is always assumed to be full descending. table 3-21. push and pop instructions l b thumb assembler arm equivalent action 0 0 push { rlist } stmdb r13!, { rlist } push the registers specified by rlist onto the stack. update the stack pointer. 0 1 push { rlist, lr } stmdb r13!, { rlist, r14} push the link register and the registers specified by rlist (if any) onto the stack. update the stack pointer. 1 0 pop { rlist } ldmia r13!, { rlist } pop values off the stack into the registers specified by rlist. update the stack pointer. 1 1 pop { rlist, pc } ldmia r13!, {rlist, r15} pop values off the stack and load into the registers specified by rlist. pop the pc off the stack. update the stack pointer.
S3C4530A instructio n set 3- 89 instruction cycle times all instructions in this format have an equivalent arm instruction as shown in table 3-21. the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. examples push {r0?r4,lr} ; store r0, r1, r2, r3, r4 and r14 (lr) at ; the stack pointed to by r13 (sp) and update r13. ; useful at start of a sub-routine to ; save workspace and return address. pop {r2, r6, pc} ; load r2, r6 and r15 (pc) from the stack ; pointed to by r13 (sp) and update r13. ; useful to restore workspace and return from sub-routine.
instruction set s3c 4530a 3- 90 format 15: multiple load/store [7:0] register list [10:8] base register [11] load/store bit 0 = store to memory 1 = load from memory 15 0 1 14 10 1 0 13 12 11 rlist 0 l 7 8 rb figure 3-44. format 15 operation these instructions allow multiple loading and storing of lo registers. the thumb assembler syntax is shown in the following table. table 3-22. the multiple load/store instructions l thumb assembler arm equivalent action 0 stmia rb!, { rlist } stmia rb!, { rlist } store the registers specified by rlist, starting at the base address in rb. write back the new base address. 1 ldmia rb!, { rlist } ldmia rb!, { rlist } load the registers specified by rlist, starting at the base address in rb. write back the new base address. instruction cycle times all instructions in this format have an equivalent arm instruction as shown in table 3-22. the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. examples stmia r0!, {r3-r7} ; store the contents of registers r3-r7 ; starting at the address specified in ; r0, incre menting the addresses for each word. ; write back the updated value of r0.
S3C4530A instructio n set 3- 91 format 16: conditional branch [7:0] 8-bit signed immediate [11:8] condition 15 0 1 14 1 0 13 12 11 soffset 8 1 7 8 cond figure 3-45. format 16 operation the instructions in this group all perform a conditional branch depending on the state of the cpsr condition codes. the branch offset must take account of the prefetch operation, which causes the pc to be 1 word (4 bytes) ahead of the current instruction. the thumb assembler syntax is shown in the following table. table 3-23. the conditional branch instructions code thumb assembler arm equivalent action 0000 beq label beq label branch if z set (equal) 0001 bne label bne label branch if z clear (not equal) 0010 bcs label bcs label branch if c set (unsigned higher or same) 0011 bcc label bcc label branch if c clear (unsigned lower) 0100 bmi label bmi label branch if n set (negative) 0101 bpl label bpl label branch if n clear (positive or zero) 0110 bvs label bvs label branch if v set (overflow) 0111 bvc label bvc label branch if v clear (no overflow) 1000 bhi label bhi label branch if c set and z clear (unsigned higher) 1001 bls label bls label branch if c clear or z set (unsigned lower or same) 1010 bge label bge label branch if n set and v set, or n clear and v clear (greater or equal)
instruction set s3c 4530a 3- 92 table 3-23. the conditional branch instructions (continued) code thumb assembler arm equivalent action 1011 blt label blt label branch if n set and v clear, or n clear and v set (less than) 1100 bgt label bgt label branch if z clear, and either n set and v set or n clear and v clear (greater than) 1101 ble label ble label branch if z set, or n set and v clear, or n clear and v set (less than or equal) notes: 1. while label specifies a full 9-bit two?s complement address, this must always be half-word-aligned (ie with bit 0 set to 0) since the assembler actually places label >> 1 in field soffset8. 2. cond = 1110 is undefined, and should not be used. cond = 1111 creates th e swi instruction: see . instruction cycle times all instructions in this format have an equivalent arm instruction as shown in table 3-23. the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. examples cmp r0, #45 ; branch to over-if r0 > 45. bgt over ; note that the thumb opcode will contain ... ; the number of half-words to offset. ... over ... ; must be half-word alig ned. ...
S3C4530A instructio n set 3- 93 format 17: software interrupt [7:0] comment field 15 0 1 14 1 0 13 12 11 value 8 1 7 8 10 9 1 1 1 1 figure 3-46. format 17 operation the swi instruction performs a software interrupt. on taking the swi, the processor switches into arm state and enters supervisor (svc) mode. the thumb assembler syntax for this instruction is shown below. table 3-24. the swi instruction thumb assembler arm equivalent action swi value 8 swi value 8 perform software interrupt: move the address of the next instruction into lr, move cpsr to spsr, load the swi vector address (0x8) into the pc. switch to arm state and enter svc mode. note: value 8 is used solely by the swi handler; it is ignored by the processor. instruction cycle times all instructions in this format have an equivalent arm instruction as shown in table 3-24. the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. examples swi 18 ; take the software interrupt exception. ; enter supervisor mode with 18 as the ; requested swi number.
instruction set s3c 4530a 3- 94 format 18: unconditional branch [10:0] immediate value 15 0 1 14 1 1 13 12 11 offset11 0 10 0 figure 3-47. format 18 operation this instruction performs a pc-relative branch. the thumb assembler syntax is shown below. the branch offset must take account of the prefetch operation, which causes the pc to be 1 word (4 bytes) ahead of the current instruction. table 3-25. summary of branch instruction thumb assembler arm equivalent action b label bal label (half-word offset) branch pc relative +/- offset11 << 1, where label is pc +/- 2048 bytes. note: the address specified by label is a full 12-bit two s complement address, but must always be half-word aligned (ie bit 0 set to 0), since the assembler places label >> 1 in the offset11 field. examples here b here ; branch onto itself. assembles to 0xe7fe. ; (note effect of pc offset). b jimmy ; branch to 'jimmy'. ... ; note that the thumb opcode will conta in the number of ; half-words to offset. jimmy ... ; must be half-word aligned.
S3C4530A instructio n set 3- 95 format 19: long branch with link [10:0] long branch and link offset high/low [11] low/high offset bit 0 = offset high 1 = offset low 15 0 1 14 1 1 13 12 11 offset 1 10 h figure 3-48. format 19 operation this format specifies a long branch with link. the assembler splits the 23-bit two?s complement half-word offset specified by the label into two 11-bit halves, ignoring bit 0 (which must be 0), and creates two thumb instructions. instruction 1 (h = 0) in the first instruction the offset field contains the upper 11 bits of the target address. this is shifted left by 12 bits and added to the current pc address. the resulting address is placed in lr. instruction 2 (h =1) in the second instruction the offset field contains an 11-bit representation lower half of the target address. this is shifted left by 1 bit and added to lr. lr, which now contains the full 23-bit address, is placed in pc, the address of the instruction following the bl is placed in lr and bit 0 of lr is set. the branch offset must take account of the prefetch operation, which causes the pc to be 1 word (4 bytes) ahead of the current instruction.
instruction set s3c 4530a 3- 96 instruction cycle times this instruction format does not have an equivalent arm instruction. table 3-26. the bl instruction h thumb assembler arm equivalent action 0 bl label none lr := pc + offsethigh << 12 1 temp := next instruction address pc := lr + offsetlow << 1 lr := temp | 1 examples bl faraway ; unconditionally branch to 'faraw ay' next ... ; and place following instruction ; address, ie ?next?, in r14,the link ; register and set bit 0 of lr high. ; note that the thumb opcodes will ; contain the number of half-words to offset. faraway ... ; must be half-word aligned.
S3C4530A instructio n set 3- 97 instruction set examples the following examples show ways in which the thumb instructions may be used to generate small and efficient code. each example also shows the arm equivalent so these may be compared. multiplication by a constant using shifts and adds the following shows code to multiply by various constants using 1, 2 or 3 thumb instructions alongside the arm equivalents. for other constants it is generally better to use the built-in mul instruction rather than using a sequence of 4 or more instructions. thumb arm 1. multiplication by 2^n (1,2,4,8,...) lsl ra, rb, lsl #n ; mov ra, rb, lsl #n 2. multiplication by 2^n+1 (3,5,9,17,...) lsl rt, rb, #n ; add ra, rb, rb, lsl #n add ra, rt, rb 3. multiplication by 2^n-1 (3,7,15,...) lsl rt, rb , #n ; rsb ra, rb, rb, lsl #n sub ra, rt, rb 4. multiplication by -2^n (-2, -4, -8, ...) lsl ra, rb, #n ; mov ra, rb, lsl #n mvn ra, ra ; rsb ra, ra, #0 5. multiplication by -2^n-1 (-3, -7, -15, ...) lsl rt, rb, #n ; sub ra, rb, rb, lsl #n sub ra, rb, rt multiplication by any c = {2^n+1, 2^n-1, -2^n or -2^n-1} * 2^n effectively this is any of the multiplications in 2 to 5 followed by a final shift. this allows the following additional constants to be multiplied. 6, 10, 12, 14, 18, 20, 24, 28, 30, 34, 36, 40, 48, 56, 60, 62 ..... (2..5) ; (2..5) lsl ra, ra, #n ; mov ra, ra, lsl #n
instruction set s3c 4530a 3- 98 general purpose signed divide this example shows a general purpose signed divide and remainder routine in both thumb and arm code. thumb code ;signed_divide ; signed divide of r1 by r0: returns quotient in r0, ; remainder in r1 ;get abs value of r0 into r3 asr r2, r0, #31 ; get 0 or -1 in r2 depending on sign of r0 eor r0, r2 ; eor with -1 (0xffffffff) if negative sub r3, r0, r2 ; and add 1 (sub -1) to get abs valu e ;sub always sets flag so go & report division by 0 if necessary beq divide_by_zero ;get abs value of r1 by xoring with 0xffffffff and adding 1 if negative asr r0, r1, #31 ; get 0 or -1 in r3 depending on sign of r1 eor r1, r0 ; eor with -1 (0xffffffff) if negative sub r1, r0 ; and add 1 (sub -1) to get abs value ;save signs (0 or -1 in r0 & r2) for later use in determining ; sign of quotient & remainder. push {r0, r2} ;justification, shift 1 bit at a time until divisor (r0 value) ; is just <= than dividend (r1 value). to do this shift dividend ; right by 1 and stop as soon as shifted value becomes >. lsr r0, r1, #1 mov r2, r3 b %ft0 just_l lsl r2, #1 0 cmp r2, r0 bls just_l mov r0, #0 ; set accumulator to 0 b %ft0 ; branch into division loop div_l lsr r2, #1 0 cmp r1, r2 ; test subtract bcc %ft0 sub r1, r2 ; if successful do a real subtract 0 adc r0, r0 ; shift result and add 1 if subtract succeeded cmp r2, r3 ; terminate when r2 == r3 (ie we have just bne div_l ; tested subtracting the 'ones' value). ;now fix up the signs of the quotient (r0) and remainder (r1) pop {r2, r3} ; get dividend/divisor signs back eor r3, r2 ; result sign eor r0, r3 ; negate if result sign = -1 sub r0, r3 eor r1, r2 ; negate remainder if dividend sign = -1 sub r1, r2 mov pc, lr
S3C4530A instructio n set 3- 99 arm code signed_divide ; effectively zero a4 as top bit will be shifted out later ands a4, a1, #&80000000 rsbmi a1, a1, #0 eors ip, a4, a2, asr #32 ;ip bit 31 = sign of result ;ip bit 30 = sign of a2 rsbcs a2, a2, #0 ;central part is identical code to udiv (without mov a4, #0 which comes for free as part of signed entry sequence) movs a3, a1 beq divide_by_zero just_l ; justification stage shifts 1 bit at a time cmp a3, a2, lsr #1 movls a3, a3, lsl #1 ; nb: lsl #1 is always ok if ls succeeds blo s_loop div_l cmp a2, a3 adc a4, a4, a4 subcs a2, a2, a3 teq a3, a1 movne a3, a3, lsr #1 bne s_loop2 mov a1, a4 movs ip, ip, asl #1 rsbcs a1, a1, #0 rsbmi a2, a2, #0 mov pc, lr
instruction set s3c 4530a 3- 100 division by a constant division by a constant can often be performed by a short fixed sequence of shifts, adds and subtracts. here is an example of a divide by 10 routine based on the algorithm in the arm cookbook in both thumb and arm code. thumb code udiv10 ; take argument in a1 returns quotient in a1, ; remainder in a2 mov a2, a1 lsr a3, a1, #2 sub a1, a3 lsr a3, a1, #4 add a1, a3 lsr a3, a1, #8 add a1, a3 lsr a3, a1, #16 add a1, a3 lsr a1, #3 asl a3, a1, #2 add a3, a1 asl a3, #1 sub a2, a3 cmp a2, #10 blt %ft0 add a1, #1 sub a2, #10 0 mov pc, lr arm code udiv10 ; take argument in a1 returns quotient in a1, ; remainder in a2 sub a2, a1, #10 sub a1, a1, a1, lsr #2 add a1, a1, a1, lsr #4 add a1, a1, a1, lsr #8 add a1, a1, a1, lsr #16 mov a1, a1, lsr #3 add a3, a1, a1, asl #2 subs a2, a2, a3, asl #1 addpl a 1, a1, #1 addmi a2, a2, #10 mov pc, lr
S3C4530A system man ager 4- 1 4 system manager overview the S3C4530A system manager has the following functions. ? to arbitrate system bus access requests from several master blocks based on fixed priorities or round-robin method by sysconf[3] register value. ? to provide the required memory control signals for external memory accesses. for example, if a master block such as the dma controller or the cpu generates an address that corresponds to a dram bank, the system manager's dram controller generates the required normal/edo or sdram access signals. the interface signals for normal/edo or sdram can be switched by syscfg[31]. ? to provide the required signals for bus traffic between the S3C4530A and rom/sram and the external i/o banks. ? to compensate for differences in bus width for data flowing between the external memory bus and the internal data bus. ? S3C4530A supports both little and big endian for external memory or i/o devices. note by generating an external bus request, an external device can access the S3C4530A's external memory interface pins. in addition, the S3C4530A can access slow external devices by using a wait signal. the wait signal, which is generated by the external device, extends the duration of the cpu?s memory access cycle beyond its programmable value.
system manager s3c4 530a 4- 2 system manager registers to control the external memory operations, the system manager uses a dedicated set of special registers (see table 4-1). by programming the values in the system manager special registers, you can specify such things as ? memory type ? external bus width access cycle ? control signal timing (ras and cas, for example) ? memory bank locations ? the sizes of memory banks to be used for arbitrary address spacing the system manager uses some special registers to control the generation and processing of the control signals, addresses, and data that are required by the external devices in a standard system configuration. the special registers are also used to control access to six banks of rom/sram/flash, four banks of dram, four banks of the external i/o banks, and a special register mapping area. the address resolution for each memory bank base pointer is 1m bytes (20 bits) and the base address pointer is 6 bits. this gives a total addressable memory bank space of 16 m words. note when writing a value to a memory bank control register from romcon0 to refextcon (locations 0x3014 to 0x303c), as shown in table 4-1, you must always set the register using a single stm (store multiple) instruction. additionally, the address spaces for successive memory banks must not overlap in the system memory map.
S3C4530A system man ager 4- 3 16k words-4m words (32 bits) addr [21:0] 64k words (fixed for all i/o banks) continuous 256k word space for 4 external i/o banks 16k words (fixed) 0, 4 or 8k bytes (fixed) 0x3ffffff 16m words (16m x 32 bits) sa [25:0] 0x0000000 reserved special register bank internal sram external i/o bank 3 external i/o bank 2 external i/o bank 1 external i/o bank 0 dram/sdram bank 3 dram/sdram bank 2 dram/sdram bank 1 dram/sdram bank 0 rom/sram/flash bank 5 rom/sram/flash bank 4 rom/sram/flash bank 3 rom/sram/flash bank 2 rom/sram/flash bank 1 rom/sram/flash bank 0 note: you can define banks anywhere within the 64-mbyte address space. figure 4-1. S3C4530A system memory map
system manager s3c4 530a 4- 4 system memory map following are several important features to note about the S3C4530A system memory map: ? the size and location of each memory bank is determined by setting the registers for "current bank base pointer" and "current bank end pointer". you can use this base/next bank pointer concept to set up a consecutive memory map. to do this, you set the base pointer of the "next bank" to the same address as the next pointer of the "current bank". please note that when setting the bank control registers, the address boundaries of consecutive banks must not overlap. this rule should be applied even if one or more banks are disabled. ? four external i/o banks are defined in a continuous address space. a programmer can only set the base pointer for external i/o bank 0. then, the start address of the external i/o bank 1 is the start address of the external i/o bank 0 + 256kb. similarly, the start address of the external i/o bank 2 is the start address of the external i/o bank 0 + 512kb, and the start address of the external i/o bank 3 is the start address of the external i/o bank 0 + 768kb. therefore, the total consecutive addressable space of the four external i/o banks is defined as the start address of the external i/o bank 0 + 1024kb. ? within the addressable space, the start address of each i/o bank is not fixed. you can use bank control registers to assign a specific bank start address by setting the bank?s base pointer. the address resolution is 1m bytes. the bank?s start address is defined as "base pointer << 20" and the bank?s end address (except for external i/o banks) is "next pointer << 20 - 1". after a power-on or system reset, all bank address pointer registers are initialized to their default values. in this case, all bank pointers except for the next pointer of rom/sram/flash bank 0 are set to zero. this means that, except for rom/sram/flash bank 0, all banks are undefined following a system startup. the reset values for the next pointer and the base pointer of rom/sram/flash bank 0 are 0x200 and 0x000, respectively. this means that a system reset automatically defines rom/sram/flash bank 0 as a 32-mbyte space with a start address of zero. this initial definition of rom/sram/flash bank 0 lets the system power-on or reset operation pass control to the user-supplied boot code that is stored in the external rom. (this code is located at address 0 in the system memory map.) when the boot code (i.e. rom program) is executed, it performs various system initialization tasks and reconfigures the system memory map according to the application?s actual external memory and device configuration. the initial system memory map following system start-up is shown in figure 4-2.
S3C4530A system man ager 4- 5 0x3ffffff special function registers rom/sram/flash bank 0 area (non-accessible) undefined area rom/sram/flash bank 0 area (accessible) 0x3ff0000 0x2000000 0x0000000 4 m address [21:0] 32 m 64 m bytes sa [25:0] figure 4-2. initial system memory map (after reset) table 4-1. system manager registers registers offset r/w description reset value syscfg 0x0000 r/w system configuration register 0x4fffff91 clkcon 0x3000 r/w clock control register 0x00000000 extacon0 0x3008 r/w external i/o timing register 1 0x00000000 extacon1 0x300c r/w external i/o timing register 2 0x00000000 extdbwth 0x3010 r/w data bus width of each bank 0x00000000 romcon0 0x3014 r/w rom/sram/flash bank 0 control register 0x20000060 romcon1 0x3018 r/w rom/sram/flash bank 1 control register 0x00000060 romcon2 0x301c r/w rom/sram/flash bank 2 control register 0x00000060 romcon3 0x3020 r/w rom/sram/flash bank 3 control register 0x00000060 romcon4 0x3024 r/w rom/sram/flash bank 4 control register 0x00000060 romcon5 0x3028 r/w rom/sram/flash bank 5 control register 0x00000060 dramcon0 0x302c r/w dram bank 0 control register 0x00000000 dramcon1 0x3030 r/w dram bank 1 control register 0x00000000 dramcon2 0x3034 r/w dram bank 2 control register 0x00000000 dramcon3 0x3038 r/w dram bank 3 control register 0x00000000 refextcon 0x303c r/w refresh and external i/o control register 0x000083ed
system manager s3c4 530a 4- 6 external address translation method depends on the width of external memory the S3C4530A address bus is, in some respects, different than the bus used in other standard cpus. based on the required data bus width of each memory bank, the internal system address bus is shifted out to an external address bus, addr[21:0]. this means that the memory control signals such as nras[3:0], ncas[3:0], necs[3:0], nrcs[5:0], and nwbe[3:0] are generated by the system manager according to a pre-configured external memory scheme (see table 4-2). this is applied to sdram signals as same method. table 4-2. address bus generation guidelines data bus width external address pins, addr[21:0] accessible memory size 8-bit a21?a0 (internal) 4m bytes 16-bit a22?a1 (internal) 4m half-words 32-bit a23?a2 (internal) 4m words data bus width configuration (8-bit/16-bit/32-bit) 8-bit 16-bit 32-bit system address bus: sa [25:0] 22-bit 22-bit 22-bit 22-bit internal external sa [21:0] sa [22:1] sa [23:2] external address pins addr [21:0] figure 4-3. external address bus diagram
S3C4530A system man ager 4- 7 connection of external memory with various data width as another example, let us see how the S3C4530A maps cpu address spaces to physical addresses in external memory: when the cpu issues an arbitrary address to access an external memory device, the S3C4530A compares the upper 5 bits of the issued address with the address pointers of all memory banks. it does this by consecutively subtracting each address pointer value from the cpu address. there are two reasons why this subtraction method is used: ? to check the polarities of the subtraction result so as to identify which bank corresponds to the address issued by the cpu. ? to derive the offset address for the corresponding bank. when the bank is identified and the offset has been derived, the corresponding bank selection signal (nrcs[5:0], or necs[3:0]) is generated, and the derived offset is driven to address external memory through the S3C4530A physical address bus. the S3C4530A can be configured as big-endian or little-endian mode by external little/big selection pin (little, 49). in big endian mode, the most significant byte of the external memory data is stored at the lowest numbered byte and the least significant byte at the highest numbered byte. for example, in case of the external word memory system, byte 0 of the memory is connected to data lines 31 through 24, d[31:24]. in little endian mode, vice versa. (see figure 4-4 external memory interface)
system manager s3c4 530a 4- 8 endian modes S3C4530A supports both little-endian and big-endian for external memory or i/o devices by setting the pin little (pin 49). the system diagram for S3C4530A is shown in S3C4530A cpu (arm7tmdi) cpu addr. cpu data bus 0 31 memory controller special register cpu register sa (addr.) sd (data) addr xdata 0 31 0 31 bit number ...x0 ...x4 ...x8 ...xc word address external memory figure 4-4. data bus connection with external memory below tables(4-3 through 4-14) are show the program/data path between the cpu register and the external memory using little-/big-endian and word/half-word/byte access.
S3C4530A system man ager 4- 9 table 4-3 and 4-4. using big-endian and word access, program/data path between register and external memory. wa=address whose lsb is 0, 4, 8, c x=don't care cas3-0/nwbe3-0=0 means active and 1 means inactive table 4-3. word access store operation with big-endian store (cpu reg ? external memory) ext. memory type word half word byte bit num. cpu register data 31 0 abcd 31 0 abcd 31 0 abcd cpu address wa wa wa bit num. cpu data bus 31 0 abcd 31 0 abcd 31 0 abcd 31 0 abcd 31 0 abcd 31 0 abcd 31 0 abcd bit num. internal sd bus 31 0 abcd 31 0 abcd 31 0 abcd 31 0 abcd 31 0 abcd 31 0 abcd 31 0 abcd external address wa wa wa + 2 wa wa + 1 wa + 2 wa + 3 cas3-0/nwbe3-0 0000 xx00 xx00 xxx0 xxx0 xxx0 xxx0 bit num. xdata 31 0 abcd 15 0 ab 15 0 cd 7 0 a 7 0 b 7 0 c 7 0 d bit num. ext. memory data 31 0 abcd 15 0 ab 15 0 cd 7 0 a 7 0 b 7 0 c 7 0 d timing sequence 1st write 2nd write 1st write 2nd write 3rd write 4th write table 4-4 word access load operation with big-endian load (cpu reg ? external memory) ext. memory type word half word byte bit num. cpu register data 31 0 abcd 31 0 abcd 31 0 abcd cpu address wa wa wa bit num. cpu data bus 31 0 abcd 31 0 abxx 31 0 abcd 31 0 axxx 31 0 abxx 31 0 abcx 31 0 abcd bit num. internal sd bus 31 0 abcd 31 0 abxx 31 0 abcd 31 0 axxx 31 0 abxx 31 0 abcx 31 0 abcd external address wa wa wa + 2 wa wa + 1 wa + 2 wa + 3 cas3-0/nwbe3-0 0000 xx00 xx00 xxx0 xxx0 xxx0 xxx0 bit num. xdata 31 0 abcd 15 0 ab 15 0 cd 7 0 a 7 0 b 7 0 c 7 0 d bit num. ext. memory data 31 0 abcd 15 0 ab 15 0 cd 7 0 a 7 0 b 7 0 c 7 0 d timing sequence 1st read 2nd read 1st read 2nd read 3rd read 4th read
system manager s3c4 530a 4- 10 table 4-5 and 4-6. using big-endian and half-word access, program/data path between register and external memory. ha=address whose lsb is 0, 2, 4, 6, 8, a, c, e hal=address whose lsb is 0, 4, 8, c hau=address whose lbs is 2, 6, a, e x=don't care, cas3-0/nwbe3-0=0 means active and 1 means inactive table 4-5. half-word access store operation with big-endian store (cpu reg ? external memory) ext. memory type word half word byte bit num. cpu register data 31 0 abcd 31 0 abcd 31 0 abcd cpu address hal hau ha ha bit num. cpu data bus 31 0 cdcd 31 0 cdcd 31 0 cdcd 31 0 cdcd 31 0 cdcd bit num. internal sd bus 31 0 cdcd 31 0 cdcd 31 0 cdcd 31 0 cdcd 31 0 cdcd external address hal hal ha ha ha + 1 cas3-0/nwbe3-0 0011 1100 xx00 xxx0 xxx0 bit num. xdata 31 0 cdxx 31 0 xxcd 15 0 cd 7 0 c 7 0 d bit num. ext. memory data 31 16 cd 15 0 cd 15 0 cd 7 0 c 7 0 d timing sequence 1st write 2nd write table 4-6. half-word access load operation with big-endian load (cpu reg ? external memory) ext. memory type word half word byte bit num. cpu register data 15 0 ab 15 0 cd 15 0 ab 15 0 ab cpu address hal hau ha ha bit num. cpu data bus 31 0 abab 31 0 cdcd 31 0 abab 31 0 axax 31 0 abab bit num. internal sd bus 31 0 abab 31 0 cdcd 31 0 abab 31 0 axax 31 0 abab external address hal hal ha ha ha + 1 cas3-0/nwbe3-0 xxxx xxxx xxxx xxxx xxxx bit num. xdata 31 0 abcd 31 0 abcd 15 0 ab 7 0 a 7 0 b bit num. ext. memory data 31 0 abcd 15 0 ab 7 0 a 7 0 b timing sequence 1st read 2nd read
S3C4530A system man ager 4- 11 table 4-7 and 4-8. using big-endian and byte access, program/data path between register and external memory. ba=address whose lsb is 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, a, b, c, d, e, f bal=address whose lsb is 0, 2, 4, 6, 8, a, c, e bau=address whose lbs is 1, 3, 5, 7, 9, b, d, f ba0=address whose lsb is 0, 4, 8, c ba1=address whose lbs is 1, 5, 9, d ba2=address whose lsb is 2, 6, a, e ba3=address whose lbs is 3, 7, b, f x=don't care cas3-0/nwbe3-0=0 means active and 1 means inactive table 4-7. byte access store operation with big-endian store (cpu reg ? external memory) ext. memory type word half word byte bit num. cpu register data 31 0 abcd 31 0 abcd 31 0 abcd cpu address ba0 ba1 ba2 ba3 bal bau ba bit num. cpu data bus 31 0 dddd 31 0 dddd 31 0 dddd 31 0 dddd 31 0 dddd 31 0 dddd 31 0 dddd bit num. internal sd bus 31 0 dddd 31 0 dddd 31 0 dddd 31 0 dddd 31 0 dddd 31 0 dddd 31 0 dddd external address ba0 ba0 ba0 ba0 bal bal ba cas3-0/nwbe3-0 0111 1011 1101 1110 xx10 xx01 xxx0 bit num. xdata 31 0 dxxx 31 0 xdxx 31 0 xxdx 31 0 xxxd 15 0 dx 15 0 xd 7 0 d bit num. ext. memory data 31 24 d 23 16 d 15 8 d 7 0 d 15 0 d 15 0 d 7 0 d table 4-8. byte access load operation with big-endian load (cpu reg ? external memory) ext. memory type word half word byte bit num. cpu register data 7 0 a 7 0 b 7 0 c 7 0 d 7 0 a 7 0 b 7 0 a cpu address ba0 ba1 ba2 ba3 bal bau ba bit num. cpu data bus 31 0 aaaa 31 0 bbbb 31 0 cccc 31 0 dddd 31 0 aaaa 31 0 bbbb 31 0 aaaa bit num. internal sd bus 31 0 aaaa 31 0 bbbb 31 0 cccc 31 0 dddd 31 0 aaaa 31 0 bbbb 31 0 aaaa external address ba0 ba0 ba0 ba0 bal bal ba cas3-0/nwbe3-0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx bit num. xdata 31 0 abcd 31 0 abcd 31 0 abcd 31 0 abcd 15 0 ab 15 0 ab 7 0 a bit num. ext. memory data 31 0 abcd 15 0 ab 7 0 a
system manager s3c4 530a 4- 12 table 4-9 and 4-10. using little-endian and word access, program/data path between register and external memory. wa=address whose lsb is 0, 4, 8, c x=don't care cas3-0/nwbe3-0=0 means active and 1 means inactive table 4-9. word access store operation with little-endian store (cpu reg ? external memory) ext. memory type word half word byte bit num. cpu register data 31 0 abcd 31 0 abcd 31 0 abcd cpu address wa wa wa bit num. cpu data bus 31 0 abcd 31 0 abcd 31 0 abcd 31 0 abcd 31 0 abcd 31 0 abcd 31 0 abcd bit num. internal sd bus 31 0 abcd 31 0 abcd 31 0 abcd 31 0 abcd 31 0 abcd 31 0 abcd 31 0 abcd external address wa wa wa + 2 wa wa + 1 wa + 2 wa + 3 bit num. xdata 31 0 abcd 15 0 cd 15 0 ab 7 0 d 7 0 c 7 0 b 7 0 a bit num. ext. memory data 31 0 abcd 15 0 cd 15 0 ab 7 0 d 7 0 c 7 0 b 7 0 a timing sequence 1st write 2nd write 1st write 2nd write 3rd write 4th write table 4-10. word access load operation with little-endian load (cpu reg ? external memory) ext. memory type word half word byte bit num. cpu register data 31 0 abcd 31 0 abcd 31 0 abcd cpu address wa wa wa bit num. cpu data bus 31 0 abcd 31 0 xxcd 31 0 abcd 31 0 xxxd 31 0 xxcd 31 0 xbcd 31 0 abcd bit num. internal sd bus 31 0 abcd 31 0 xxcd 31 0 abcd 31 0 xxxd 31 0 xxcd 31 0 xbcd 31 0 abcd external address wa wa wa + 2 wa wa + 1 wa + 2 wa + 3 bit num. xdata 31 0 abcd 15 0 cd 15 0 ab 7 0 d 7 0 c 7 0 b 7 0 a bit num. ext. memory data 31 0 abcd 15 0 cd 15 0 ab 7 0 d 7 0 c 7 0 b 7 0 a timing sequence 1st read 2nd read 1st read 2nd read 3rd read 4th read
S3C4530A system man ager 4- 13 table 4-11 and 4-12. using little-endian and half-word access, program/data path between register and external memory. ha=address whose lsb is 0, 2, 4, 6, 8, a, c, e hal=address whose lsb is 0, 4, 8, c hau=address whose lbs is 2, 6, a, e x=don't care cas3-0/nwbe3-0=0 means active and 1 means inactive table 4-11. half-word access store operation with little-endian store (cpu reg ? external memory) ext. memory type word half word byte bit num. cpu register data 31 0 ab cd 31 0 abcd 31 0 abcd cpu address hal hau ha ha bit num. cpu data bus 31 0 cdcd 31 0 cdcd 31 0 cdcd 31 0 cdcd 31 0 cdcd bit num. internal sd bus 31 0 cdcd 31 0 cdcd 31 0 cdcd 31 0 cdcd 31 0 cdcd external address hal hal ha ha ha+1 cas3-0/nwbe3-0 1100 0011 xx00 xxx0 xxx0 bit num. xdata 31 0 cdcd 31 0 cdcd 15 0 cd 7 0 d 7 0 c bit num. ext. memory data 15 0 cd 31 16 cd 15 0 cd 7 0 d 7 0 c timing sequence 1st write 2nd write table 4-12. half-word access load operation with little-endian load (cpu reg ? external memory) ext. memory type word half word byte bit num. cpu register data 15 0 cd 15 0 ab 15 0 ab 15 0 ab 15 0 ba cpu address hal hau ha ha bit num. cpu data bus 31 0 cdcd 31 0 abab 31 0 abab 31 0 xaxa 31 0 baba bit num. internal sd bus 31 0 cdcd 31 0 abab 31 0 abab 31 0 xaxa 31 0 baba external address hal hal ha ha ha+1 cas3-0/nwbe3-0 xxxx xxxx xxxx xxxx xxxx bit num. xdata 31 0 abcd 31 0 abcd 15 0 ab 7 0 a 7 0 b bit num. ext. memory data 31 0 abcd 15 0 ab 7 0 a 7 0 b timing sequence 1st read 2nd read
system manager s3c4 530a 4- 14 table 4-13 and 4-14. using little-endian and byte access, program/data path between register and external memory. ba=address whose lsb is 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, a, b, c, d, e, f bal=address whose lsb is 0, 2, 4, 6, 8, a, c, e bau=address whose lbs is 1, 3, 5, 7, 9, b, d, f ba0=address whose lsb is 0, 4, 8, c ba1=address whose lbs is 1, 5, 9, d ba2=address whose lsb is 2, 6, a, e ba3=address whose lbs is 3, 7, b, f x=don't care cas3-0/nwbe3-0=0 means active and 1 means inactive table 4-13. byte access store operation with little-endian store (cpu reg ? external memory) ext. memory type word half word byte bit num. cpu register data 31 0 abcd 31 0 abcd 31 0 abcd cpu address ba0 ba1 ba2 ba3 bal bau ba bit num. cpu data bus 31 0 dddd 31 0 dddd 31 0 dddd 31 0 dddd 31 0 dddd 31 0 dddd 31 0 dddd bit num. internal sd bus 31 0 dddd 31 0 dddd 31 0 dddd 31 0 dddd 31 0 dddd 31 0 dddd 31 0 dddd external address ba0 ba0 ba0 ba0 bal bal ba cas3-0/nwbe3-0 1110 1101 1011 0111 xx10 xx01 xxx0 bit num. xdata 31 0 xxxd 31 0 xxdx 31 0 xdxx 31 0 d xxx 15 0 xd 15 0 dx 15 0 d bit num. ext. memory data 7 0 d 15 8 d 23 16 d 31 24 d 7 0 d 15 8 d 7 0 d table 4-14. byte access load operation with little-endian load (cpu reg ? external memory) ext. memory type word half word byte bit num. cpu register data 7 0 d 7 0 c 7 0 b 7 0 a 7 0 b 7 0 a 7 0 a cpu address ba0 ba1 ba2 ba3 bal bau ba bit num. cpu data bus 31 0 dddd 31 0 cccc 31 0 bbbb 31 0 aaaa 31 0 bbbb 31 0 aaaa 31 0 aaaa bit num. internal sd bus 31 0 dddd 31 0 cccc 31 0 bbbb 31 0 aaaa 31 0 bbbb 31 0 aaaa 31 0 aaaa external address ba0 ba0 ba0 ba0 bal bal ba cas3-0/nwbe3-0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx bit num. xdata 31 0 abcd 31 0 abcd 31 0 abcd 31 0 abcd 15 0 ab 15 0 ab 7 0 a bit num. ext. memory data 31 0 abcd 15 0 ab 7 0 a
S3C4530A system man ager 4- 15 bus arbitration in the S3C4530A micro-controller, the term "system bus" refers to the separate system address and data buses inside the chip. the S3C4530A's internal function blocks, or external devices, can request mastership of the system bus and then hold the system bus in order to perform data transfers. because the design of S3C4530A bus allows only one bus master at a time, a bus controller is required to arbitrate when two or more internal units or external devices simultaneously request bus mastership. the S3C4530A can support fixed priority and round- robin method by register setting. when the bus mastership is granted to an internal function block or an external device, other pending requests are not acknowledged until the previous bus master has released the bus. to facilitate bus arbitration, priorities are assigned to each internal S3C4530A function block. the bus controller arbitration requests for the bus mastership according to these fixed priorities. in the event of contention, mastership is granted to the function block with the highest assigned priority. in case of round-robin, bus contention does not occurred. however, external bus master request has the highest fixed priority always. fixed priorities are listed in table 4-15. note an external bus master can also be granted bus mastership and hold the S3C4530A system bus. in table 4-15, you will note that all external devices are assigned the identical priority. therefore, in the systems made up of several external devices that can become the bus master, an external circuitry must be implemented to assign additional bus arbitration priorities to all potential external bus masters. table 4-15. bus priorities for arbitration function block bus priority (group) external bus master a-1 (highest priority in group a) dram memory refresh controller a-2 general dma 1 (gdma 1) a-3 general dma 0 (gdma 0) a-4 high level data link controller b (hdlc b) a-5 high level data link controller a (hdlc a) a-6 mac buffered dma (bdma) a-7 (lowest priority in group a) writer buffer b-1 (highest priority in group b) bus router b-2 (lowest priority in group b) note : the internal function blocks are divided into two groups, group a and group b. within each group, the bus arbitration priorities are fixed according to the assigned level only when sysconf[3] set to one. in this case, if any function block is a highest priority within group, then, it can seize the system bus continuously though other function block request the system bus. if sysconf[3] set to zero, the function blocks can seize the system bus as the round-robin method. the relative priority of group a and group b is determined more or less in an alternating manner.
system manager s3c4 530a 4- 16 external bus mastership the S3C4530A can receive and acknowledge bus request signals (extmreqs) that are generated by an external bus master. when the cpu asserts an external bus acknowledge signal (extmack), the mastership is granted to the external bus master, assuming the external bus request is still active. the S3C4530A's memory interface signals become floating before the external bus acknowledge signal go to active. therefore, if the external device drive that signal as soon as received the ack, wrong data can be written to unexpected address on sdram. to avoid this, the external device should drive nsdcs to high level when ack received. and then drive that signal at the 2?nd mclko rising edge from nsdcs high level. the period between floating and ack active, the floating signal has no influence because that signals remains same address and same data for a long time. the S3C4530A does not perform dram refreshes when it is not the bus master. when an external bus master is in control of the external bus, and if it retains control for a long period of time, it must assume the responsibility of performing the necessary dram refresh operations. extmreq address, data, noe, nwbe, ndwe, nrcs, ncas, nras mclko extmack data temrh data temrs temz temar temaf figure 4-5. external bus request timing note: when external bus master requests the extmreq during the sync dram writing cycles, the extmack can be generated with the wrong writing control signals of sync dram. just floating the sync dram control signals at the time extmack , it can cause the feasible active writing on the sync dram. as the result, the wrong data can be written into unexpected address on sync dram. if this address is in the range of stack or code area, the crash will be happen sooner or later. the other memory interfaces doesn?t have this problem, which is asynchronous with mclko, that is why sync dram write cycle only. you can avoid this by disabling the sdcs (sync dram chip select high) as soon as receiving the extmack and driving the address and data after one or two mclko cycles.
S3C4530A system man ager 4- 17 control registers system configuration register (syscfg) the system manager has one system configuration register, syscfg. the syscfg register determines the start address of the system manager?s special registers and the start address of internal sram. you also use syscfg settings to control the write buffer enable, the cache enable, and the stall enable operations. all dram banks can be configured to sdram banks by setting the synchronous dram mode (syscfg[31]). note if you write a "10" into the cache mode field, syscfg[5:4], the cache enable bit is cleared automatically (see figure 4-6). table 4-16. syscfg register registers offset r/w description reset value syscfg 0x0000 r/w system configuration register 0x4fffff91
system manager s3c4 530a 4- 18 [0] stall enable (se) must be set to zero. [1] cache enable (ce) when set to "1", cache operations are enabled. [2] write buffer enable (we) when set to "1", write buffer operations are enabled. [3] fixed priority (fp) 0 = round-robin 1 = fixed priority within group [5:4] cache mode (cm) this 2-bit value determines how internal memory is to be devided into cache and sram. 00 = 4-kbyte sram, 4kbyte cache 01 = 0-kbyte sram, 8kbyte cache 10 = 8-kbyte sram, 0kbyte cache note : when you write 10 to this field, the cache enable bit is cleared automatically. [15:6] internal sram base pointer this 10-bit address becomes the upper address of sram, a25 through a16. the remaining sram address, a15 through a0, are filled with zeros. [25:16] special register bank base pointer the resolution of this value is 64k. therefore, to place the start address at 1800000h (24m), use this formula: setting value = (1800000h/64k) << 16. [30:26] product identifier (pd_id) 00001 = s3c4510x (ks32c50100) 11001 = s3c4510b 00011 = s3c4530x (ks32c50300) 10011 = S3C4530A [31] sync. dram mode 0 = normal/edo dram interface for 4 dram banks 1 = sync. dram interface for 4 dram banks. 31 0 3 4 1 2 s d m w e c e s e 25 26 30 pd_id special register bank base pointer internal sram base pointer cm 15 16 6 5 f p figure 4-6. system configuration register (syscfg)
S3C4530A system man ager 4- 19 start address setting the start address of the system manager special register area is initialized to 4fffff91h. (you can also set the start address to an arbitrary value, for example 3ff0000h.) when you have set the start address of the special register area, the register addresses are automatically defined as the start address plus the register?s offset. assume for example, that a reset initializes the start address to 3ff0000h. the offset address of the romcon register is 3014h. therefore, the physical address for romcon is 3ff0000h + 3014h = 3ff3014h. if you modified the start address of the special register area to 3000000h, the new address for the romcon register would be 3003014h. cache disable/enable to enable or disable the cache, you set the cache enable (ce) bit of the syscfg register to "1" or "0", respectively. because cache memory does not have an auto-flush feature, you must be careful to verify the coherency of data whenever you re-enable the cache. you must also carefully check any changes that the dma controller may make to data stored in memory. (usually, the memory area that is allocated to dma access operations must be non-cacheable.) the internal 8-kbyte sram can be used as a cache area. to configure this area, you use the cache mode bits, syscfg[5:4]. if you do not need to use the entire 8-kbyte area as cache, you can use the remaining area as internal sram. this area is accessed using the address of the base pointer in the internal sram field. write buffer disable/enable the S3C4530A has four programmable write buffer registers that are used to improve the speed of memory write operations. when you enable a write buffer, the cpu writes data into the write buffer, instead of an external memory location. this saves the cycle that would normally be required to complete the external memory write operation. the four write buffers also enhance the performance of the arm7tdmi core?s store operations. to maintain data coherency between the cache and external memory, the S3C4530A uses a write-through policy. an internal 4-level write buffer compensates for performance degradation caused by write-through. (for more information, see chapter 5.) stall disable/enable stall enable bit is used when the cpu accesses data under non-sequential mode and the system clock is too fast to decode the local address within the given time. when the stall option is enabled, the cpu core logic inserts a wait about non-sequential memory access occurred. so, the cpu core has more time margin. when the stall bit disabled, the logic does not insert a wait.
system manager s3c4 530a 4- 20 system clock and mux bus control register clock control register (clkcon) there is a clock control register in the system manager. this control register is used to divide the internal system clock, so the slower clock than the system clock can be made by clock dividing value. in this register, rom bank 5 address/data mux. enable control and rom bank 0, 1, 2, 3, 4, 5 wait enable function is included. table 4-17. clkcon register registers offset r/w description reset value clkcon 0x3000 r/w clock control register 0x00000000 table 4-18. clkcon register description bit number bit name description [15:0] clock dividing value S3C4530A system clock source. if clksel is low, pll output clock is used as the S3C4530A internal system clock. if clksel is high, xclk is used as the S3C4530A internal system clock. the internal system clock is divided by this value. the clock divided is used to drive the cpu and system peripherals. only one bit can be set in clkcon[15:0], that is, the clock dividing value is defined as 1, 2, 4, 8, 16,... if all bits are zero, a non- divided clock is used. [16] rom bank 5 wait enable wait cycle will check the next cycle after a chip selection signal is activated. [17] rom bank 5 address/data mux. enable using multiplex bus at rom bank 5, this bit must be set to 1. [19:18] mux bus address cycle when the address phase of multiplexed bus is not enough long for external device to receive, the address phase can be extended by setting this bit. 00 = 1 mclk 01 = 2 mclk 10 = 3 mclk [20] rom bank 5 wait 1 cycle delay wait cycle will check the second cycle after a chip selection signal is activated. [21,23,25,27,29] rom bank 4,3,2,1,0 wait enable wait cycle will check the next cycle after the each chip selection signal is activated. [21] = rom bank 4, [23] = rom bank 3, [25] = rom bank 2 [27] = rom bank 1, [29] = rom bank 0 [22,24,26,28,30] rom bank 4,3,2,1,0 wait 1 cycle delay wait cycle will check the second cycle after the each chip election signal is activated. [21] = rom bank 4, [23] = rom bank 3, [25] = rom bank 2 [27] = rom bank 1, [29] = rom bank 0 [31] test bit this bit is for factory use only. during the normal operation, it must always be 0.
S3C4530A system man ager 4- 21 31 19 15 16 [15:0] clock diving value if all bits are 0, non-divided clock is used. only one bit can be set in clkcon[15:0]. that is, the clock diving value is defined as 1,2,4,8,16,... internal system clock, f mclk = f iclk /(clkcon+1) [16] rom bank 5 wait enable 0 = disable rom bank 5 wait. 1 = enable rom bank 5 wait. [17] rom bank 5 address/data bus mux enable 0 = normal operation 1 = enable bus multiplexing [19:18] mux bus address (tac) 00 = 1 mclk 01 = 2 mclk 10 = 3 mclk [20] rom bank 5 wait 1 cycle delay 0 = no delay 1 = 1 cycle delay [21,23,25,27,29] rom bank wait enable 0 = disable rom bank wait 1 = enable rom bank wait [21] = rom bank 4, [23] = rom bank 3 [25] = rom bank 2, [27] = rom bank 1 [29] = rom bank 0 [22,24,26,28,30] rom bank wait 1 cycle delay 0 = no delay 1 = 1 cycle delay [22] = rom bank 4, [24] = rom bank 3 [26] = rom bank 2, [28] = rom bank 1 [30] = rom bank 0 [31] test bit this bit should be always 0. clock divided value 0 18 17 20 clkcon 25 21 22 24 23 26 29 28 27 30 figure 4-7. clock control register (clkcon)
system manager s3c4 530a 4- 22 system clock the external clock input, xclk, can be used to the internal system clock by assign v dd to clksel pin. using pll as the internal system clock, clksel pin has to be assigned to v ss . in this case, the internal system clock is xclk x mf. to get 50mhz of system clock, a 10mhz external clock(xclk) must be used. pll 0: mf = 5.0 1: mf = 6.6 1 mux clock divider for low power control (clkcon) clksel tmod xclk mf (2) pdown (1) iclk internal system clock(sclk) mclk notes: 1. if clksel is 1, the pll block became to the state of power down. 2. mf means multiplication factor. 0 mclko clkoen figure 4-8. system clock circuit
S3C4530A system man ager 4- 23 for the purpose of power save, clock control register (clkcon) can be programmed at low frequency. when the internal system clock is divided by clkcon, its duty-cycle is changed. if clkcon is programmed to zero, the internal system clock remains the same as the internal clock, iclk. in other cases, the duty cycle of internal system clock is no longer 50%. figure 4-9 shows the internal system clock, sclk waveform according to the clock dividing value. iclk sclk(mclk) clkcon = 0 sclk(mclk) clkcon = 1 sclk(mclk) clkcon = 2 figure 4-9. divided system clocks timing diagram
system manager s3c4 530a 4- 24 external i/o access control registers (extacon0/1) the system manager has four external i/o access control registers. these registers correspond to up to four external i/o banks that are supported by S3C4530A. table 4-19 describes two registers that are used to control the timing of external i/o bank accesses. you can control the external i/o access cycles using either a specified value or an external wait signal, newait. to obtain access cycles that are longer than a specified value, you can delay the active time of noe or nwbe by tcos value setting. after noe or nwbe active, newait should be active previously at the first mclko rising edge. in case of rom bank, nrcs and noe/nwbe signals are activated simultaneously; that is, there is no control parameter as like tcos. as a result, newait should be valid previously at the second mclko rising edge (at the third mclko rising edge when rom bank wait 1 cycle delay value is 1) after nrcs active for the rom bank. extacon0 is used to set the access timings for external i/o banks 0 and 1. extacon1 is used to set the external access timings for i/o banks 2 and 3. note the base pointer for external i/o bank 0 is set in the refextcon register(refextcon register is in dram control registers part). table 4-19. external i/o access control register description registers offset r/w description reset value extacon0 0x3008 r/w external i/o access timing register 0 0x00000000 extacon1 0x300c r/w external i/o access timing register 1 0x00000000
S3C4530A system man ager 4- 25 [2:0] chip selection set-up time on noe/nwbe (t cos0, t cos2 ) [18:16] t cos1, t cos3 000 = 0 cycle 100 = 4 cycles 001 = 1 cycle 101 = 5 cycles 010 = 2 cycles 110 = 6 cycles 011 = 3 cycles 111 = 7 cycles [5:3] address set-up time before necs (t acs0, t acs2 ) [21:19] t acs1, t acs3 000 = 0 cycle 100 = 4 cycles 001 = 1 cycle 101 = 5 cycle 010 = 2 cycles 110 = 6 cycle 011 = 3 cycles 111 = 7 cycles [8:6] chip selection hold time on necs (t coh0, t coh2 ) [24:22] t coh1, t coh3 000 = 0 cycle 100 = 4 cycles 001 = 1 cycle 101 = 5 cycles 010 = 2 cycles 110 = 6 cycles 011 = 3 cycles 111 = 7 cycles [11:9] access cycles (noe/nwbe low time) (t acc0, t acc2 ) [27:25] t acc1, t acc3 000 = 0 cycle 100 = 4 cycles 001 = 1 cycle 101 = 5 cycles 010 = 2 cycles 110 = 6 cycles 011 = 3 cycles 111 = 7 cycles 15 0 31 0 0 30 0 0 29 0 0 28 0 0 0 0 14 0 0 13 0 0 12 0 0 11 19 16 18 27 25 22 21 24 t acc1 t acc3 t coh1 t coh3 t acs1 t acs3 t cos1 t cos3 3 2 9 6 5 8 t acc0 t acc2 t coh0 t coh2 t acs0 t acs2 t cos0 t cos2 extacon0 extacon1 figure 4-10. external i/o access control registers (extacon0, extacon1)
system manager s3c4 530a 4- 26 necs noe address data newait mclko tacs = 0 (0 cycle) tcos = 0 (0 cycle) tacc = 5 (6 cycles) tcoh = 0 (0 cycle) data fetch addr tacc data tnroe tnecs tnecs tnroe taddrh figure 4-11. external i/o read timing 1 (t coh = 0, t acc = 5, t cos = 0, t acs = 0)
S3C4530A system man ager 4- 27 necs noe address data newait mclko tacs = 1 (1 cycle) tcos = 0 (0 cycle) tacc = 4 (5 cycles) tcoh = 1 (1 cycle) data fetch addr tnecs tacc data tcoh tnroe tnroe tnecs taddrh tacs figure 4-12. external i/o read timing 2 (t coh = 1, t acc = 4, t cos = 0, t acs = 1)
system manager s3c4 530a 4- 28 necs noe address data newait mclko tacs = 1 (1 cycle) tcos = 1 (1 cycle) tacc = 1 (2 cycles) tcoh = 1 (1 cycle) data read point tnroe addr tnecs tacc tacs tcos data tcoh tnroe tnecs taddrd tws twh figure 4-13. external i/o read timing with newait (t coh = 1, t acc = 1, t cos = 1, t acs = 1) when newait is asserted for external i/o banks, it would be better to set the t cos and t coh value to minimum 1 cycle for safe operation. the newait should be valid at the first mclko rising edge after noe active. the newait de-assertion timing depends on the applied ext. i/o devices.
S3C4530A system man ager 4- 29 necs nwbe address data newait mclko tacs = 0 (0 cycle) tcos = 0 (0 cycle) tacc = 5 (6 cycles) tcoh = 0 (0 cycle) addr tnwbe tnwbe data tnecs tnecs tacc taddrd twdh taddrh twdd figure 4-14. external i/o write timing 1 (t coh = 0, t acc = 5, t cos = 0, t acs = 0)
system manager s3c4 530a 4- 30 necs nwbe address data newait mclko tacs = 1 (1 cycle) tcos = 0 (0 cycle) tacc = 4 (5 cycles) tcoh = 1 (1 cycle) tacs tcoh taddrd addr data tnecs twdd twdh tacc tnwbe tnwbe tnecs figure 4-15. external i/o write timing 2 (t coh = 1, t acc = 4, t cos = 0, t acs = 1)
S3C4530A system man ager 4- 31 necs nwbe address data newait addr mclko tacs = 1 (1 cycle) tcos = 1 (1 cycle) tacc = 1 (2 cycles) tcoh = 1 (1 cycle) tacs tcos tcoh taddrd tacc data tnecs tnecs twdd twdh tws twh tnwbe tnwbe figure 4-16. external i/o write timing with newait (t coh = 1, t acc = 1, t cos = 1, t acs = 1)
system manager s3c4 530a 4- 32 data bus width register (extdbwth) the S3C4530A has interfaces for 8/16/32-bit external roms, srams, flash memories, drams, sdrams, and external i/o ports. using data bus width register, you can set the data bus width that is required for specific external memory and external i/o banks. note in figure 4-17, the term "disable" means that the S3C4530A does not generate the access signal for the corresponding external i/o bank. table 4-20. extdbwth register description registers offset r/w description reset value extdbwth 0x3010 r/w data bus width of each bank 0x00000000
S3C4530A system man ager 4- 33 31 [1:0] data bus width for rom/sram/flash bank 0 (dsr0) dsr0 is read-only data at the b0size [1:0] pins. dsr0 is used as read-only because rom/sram/flash bank 0 is used to boot the rom while the data bus width for rom/sram/flash bank 0 is set using b0size [1:0]. 00 = not permitted 01 = byte (8 bits) 10 = half-word (16 bits) 11 = word (32 bits) [3:2] data bus width for rom/sram/flash bank 1 (dsr1) [5:4] dsr2, [7:6] dsr3, [9:8] dsr4, [11:10] dsr5 00 = disable 01 = byte (8 bits) 10 = half- word (16 bits) 11 = word (32 bits) [13:12] data bus width for dram bank 0 (dsd0) [15:14] dsd1, [17:16] dsd2, [19:18] dsd3 00 = disable 01 = byte (8 bits) 10 = half-word (16 bits) 11 = word (32 bits) [21:20] data bus width for external i/o bank 0 (dsx0) [23:22] dsx1, [25:24] dsx2, [27:26] dsx3 00 = dissable 01 = byte (8 bits) 10 = half-word (16 bits) 11 = word (32 bits) note: when you select "disable", the assigned external i/o bank access signal is not generated. 30 29 0 extdbwth 0 0 0 28 26 27 dsx3 24 25 dsx2 22 23 dsx1 20 21 dsx0 18 19 dsd3 16 17 dsd2 14 15 dsd1 12 13 dsd0 10 11 dsr5 8 9 dsr4 6 7 dsr3 4 5 dsr2 2 3 dsr1 0 1 dsr0 figure 4-17. data bus width register (extdbwth)
system manager s3c4 530a 4- 34 rom/sram/flash control registers(romcon) the system manager has six control registers for rom, sram, and flash memory (see table 4-21). these registers correspond to the up to six rom/sram/flash banks that are supported by S3C4530A. for rom/sram/flash bank 0, the external data bus width is determined by the signal at the b0size[1:0] pins: when b0size[1:0] = "01", the external bus width for rom/sram/flash bank 0 is 8 bits. when b0size[1:0] = "10", the exter nal bus width for rom/sram/flash bank 0 is 16 bits. when b0size[1:0] = "11", the external bus width for rom/sram/flash bank 0 is 32 bits. you can determine the start address of a special register's bank by the value of the corresponding "special register bank base pointer". the control register?s physical address is always the sum of the register?s bank base pointer plus the register?s offset address. note if you attach sram to a rom/sram/flash bank, you must set the page mode configuration bits, romconn[1:0], in the corresponding control register to "00" (normal rom). table 4-21. rom/sram/flash control register description registers offset r/w description reset value romcon0 0x3014 r/w rom/sram/flash bank 0 control register 0x20000060 romcon1 0x3018 r/w rom/sram/flash bank 1 control register 0x00000060 romcon2 0x301c r/w rom/sram/flash bank 2 control register 0x00000060 romcon3 0x3020 r/w rom/sram/flash bank 3 control register 0x00000060 romcon4 0x3024 r/w rom/sram/flash bank 4 control register 0x00000060 romcon5 0x3028 r/w rom/sram/flash bank 5 control register 0x00000060
S3C4530A system man ager 4- 35 31 [1:0] page mode configuration (pmc) 00 = normal rom 01 = 4-word page 10 = 8-word page 11 = 16-word page [3:2] page address access time (tpa) 00 = 5 cycles 01 = 2 cycles 10 = 3 cycles 11 = 4 cycles [6:4] programmable access cycle (tacc) 000 = disable bank 001 = 2 cycles 010 = 3 cycle 011 = 4 cycles 110 = 7 cycle 111 = reserved [19:14] rom/sram/flash bank # base pointer this value is the start address of the rom/sram/flash bank #. the start address is calculated as rom/sram/flash bank # base pointer << 20. [29:24] rom/sram/flash bank # next pointer the start address is calculated as rom/sram/flash bank # base pointer << 20. 0 0 rom/sram/flash bank # next pointer 6 4 tacc 2 3 0 1 pmc tpa romcon# 30 29 24 23 rom/sram/flash bank # base pointer 20 19 14 13 figure 4-18. rom/sram/flash control registers (romcon0 - romcon5)
system manager s3c4 530a 4- 36 nrcs tnrcs tnrcs noe address data taddrd addr mclko tacc tacc = 4 (5 cycles) data fetch point tnroe taddrh trds trdh data figure 4-19. rom/sram/flash read access timing
S3C4530A system man ager 4- 37 nrcs tnrcs noe address data taddrd addr mclko tacc tacc = 2 (3 cycles) tpa = 1 (2 cycles) pmc = 1 (4 word page) tnroe addr + 1 addr + 2 addr + 3 tnrcs tpa tpa tpa data data data data data fetch data fetch data fetch data fetch trdh trdh trdh trdh tnroe figure 4-20. rom/sram/flash page read access timing
system manager s3c4 530a 4- 38 nrcs tnrcs tnrcs nwbe address data taddrd data addr mclko tacc tacc = 4 (5 cycles) twdd tnwbe tnwbe figure 4-21. rom/sram/flash write access timing
S3C4530A system man ager 4- 39 nrcs tnrcs tnrcs nwbe address data addr mclko tacc tacc = 2 (3 cycles) tpa = 1 (2 cycles) pmc = 1 (4 word page) tpa taddrd addr + 1 taddrh data data taddrd tnwbe tnwbe figure 4-22. rom/sram/flash page write access timing
system manager s3c4 530a 4- 40 nrcs tnrcs tnrcs nwbe address data taddrd data addr mclko tacc tacc = 2 (3 cycles) tpa = 1 (2 cycles) pmc = 1 (4 word page) taddrd addr + 1 taddrh noe tnroe tnroe data data fetch note 1 note 1 page hit case: tpa page miss case: tacc tnwbe tnwbe tpa (or tacc) figure 4-23. rom/sram/flash read and write access timing
S3C4530A system man ager 4- 41 nrcs tnrcs tnrcs nwbe address data data addr mclko tacc tacc = 2 (3 cycles) tpa = 1 (2 cycles) pmc = 1 (4 word page) tpa taddrd addr + 1 taddrh noe tnroe tnroe data data fetch taddrd tnwbe tnwbe figure 4-24. rom/sram/flash write and read access timing
system manager s3c4 530a 4- 42 rom bank 5 address/data multiplexed bus and newait overview the S3C4530A has separate address and data bus. S3C4530A supports multiplexed address/data bus for low cost chips that require multiplexed bus. to support this feature, the S3C4530A has one special bank (rom bank 5) which can support address/data multiplexed bus and 4-data burst access by gdma. for this feature, you should set the mux enable bit and wait enable bit of clkcon register. you can also use rom bank 5 as normal rom bank by clearing mux enable bit of clkcon register. when you set the rom bank 5 to zero wait enable bit in the clkcon register, wait cycle can be added by newait pin for rom banks. the newait pin also can be used to add wait cycle for ext i/o bank regardless of the wait enable bit. however, in case of rom banks, it is active only by enable bit set. random access by cpu at the first cycle of rom bank 5, address comes out from data bus. therefore, any device that is connected to the rom bank 5 can get address. the rest cycle is for data. as the S3C4530A has not a dedicated address strobe signal for address phase in the data bust, you should generate address strobe signal in the application device. four-data burst access by gdma when you set fb (4-data burst enable) bit in the gdmacon register, the gdma requests 4-data burst access. when you access rom bank 5 by 4-data burst mode, the multiplexed rom bank 5 bus has only one address phase. therefore, you should internally calculate the address at the data phase. to notify the 4-data burst mode to rom bank 5 device, the addr[21] remains "1" during address phase.
S3C4530A system man ager 4- 43 1 wait nrcs[5] tnrcs tnrcs noe address data newait tac taddrd data addr mclko nwbe tnwbe tacc tnwbe tac = 0 (1 cycle) tacc = 1 (2 cycles) mux bus enable data cycle address cycle addr figure 4-25. muxed bus write access of rom/sram/flash bank 5 with newait
system manager s3c4 530a 4- 44 1 wait nrcs[5] noe address data newait tac addr mclko nwbe tac = 0 (1 cycle) tacc = 1 (2 cycles) mux bus enable address cycle data read point tacc data cycle data addr taddrd tnroe tnroe tnrcs tnrcs figure 4-26. muxed bus read access of rom/sram/flash bank 5 with newait
S3C4530A system man ager 4- 45 nrcs[5] tnrcs noe address data newait tac taddrd data 0 addr 0 mclko nwbe tnwbe tac = 0 (1 cycle) tacc = 1 (2 cycles) mux bus enable address cycle data cycle addr data 1 data 2 data 3 addr 1 addr 2 addr 3 tnwbe tnrcs tacc tacc tacc tacc figure 4-27. four-data burst mode write timing of rom/sram/flash bank 5 when gdma requests
system manager s3c4 530a 4- 46 nrcs[5] tnrcs noe address data newait tac taddrd data 0 addr 0 mclko nwbe tac = 0 (1 cycle) tacc = 1 (2 cycles) mux bus enable address cycle data cycle tnrcs addr data 1 data 2 data 3 addr 1 addr 2 addr 3 tnroe tnroe tacc tacc tacc tacc figure 4-28. four-data burst mode read timing of rom/sram/flash bank 5 when gdma requests
S3C4530A system man ager 4- 47 1 wait nrcs noe address data newait addr mclko nwbe tacc = 1 (2 cycles) data read point tacc taddrd data tnroe tnrcs tnrcs tnroe figure 4-29. rom/sram/flash banks read access with newait
system manager s3c4 530a 4- 48 1 wait nrcs noe address data newait addr mclko nwbe tacc = 1 (2 cycles) data write point tacc taddrd data tnwbe tnrcs tnrcs tnwbe figure 4-30. rom/sram/flash banks write access with newait
S3C4530A system man ager 4- 49 dram control registers the system manager has four dram control registers, dramcon0?dramcon3. these registers correspond to the up to four dram banks that are supported by S3C4530A. a fifth register, refextcon, is used to set the base pointer for external i/o bank 0. S3C4530A supports edo, normal, synchronous dram(sdram). sdram mode can be selected by setting syscfg[31]. if this bit is set to '1', all dram banks are selected sdram. otherwise, edo/fp dram banks are selected. table 4-22. dram and external i/o control register description registers offset r/w description reset value dramcon0 0x302c r/w dram bank 0 control register 0x00000000 dramcon1 0x3030 r/w dram bank 1 control register 0x00000000 dramcon2 0x3034 r/w dram bank 2 control register 0x00000000 dramcon3 0x3038 r/w dram bank 3 control register 0x00000000 refextcon 0x303c r/w refresh and external i/o control register 0x000083fd
system manager s3c4 530a 4- 50 [0] edo mode (edo) (note 1) 0 = normal dram (fast page mode dram) 1 = edo dram [2:1] cas strobe time (tcs) (note 2) 00 = 1 cycle 01 = 2 cycles 10 = 3 cycles 11 = 4 cycles [3] cas pre-charge time (tcp) (note 1) 0 = 1 cycle 1 = 2 cycles [7] ras to cas delay (trc or trcd) 0 = 1 cycle 1 = 2 cycles [9:8] ras pre-charge time (trp) 00 = 1 cycle 01 = 2 cycles 10 = 3 cycles 11 = 4 cycles [19:14] dram bank # base pointer this value indicates the start address of dram bank #. the start address is calculated as ram bank # base pointer << 20 [29:24] dram bank # next pointer the start address is calculated as dram bank # base pointer << 20 [31:30] number of column address bits in dram bank # (can) 00 = 8 bits 01 = 9 bits 10 = 10 bits 11 = 11 bits notes: 1. in sdram mode, these bits are reserved. 2. in sdram mode, tcs is fixed with one cycle. dramcon# 31 30 29 can 20 dram bank # next pointer 19 10 9 4 0 2 3 0 1 dram bank # base pointer trp tcs t c p e d o 24 23 14 13 8 6 7 t r c figure 4-31. dram control registers (dramcon0-dramcon3)
S3C4530A system man ager 4- 51 nras noe address data mclko ndwe trp = 0 (1 cycle) tcs = 1 (2 cycles) tcp = 0 (1 cycle) trc = 0 (1 cycle) ncas trp tcs tcs data data fetch (edo dram) data fetch (normal dram) data data fetch (edo dram) data fetch (normal dram) column addr tcp data data tnroe tnroe tnrasr tnrasf tncasr taddrd row addr column addr (same page) tncasf trc figure 4-32. edo/fp dram bank read timing (page mode)
system manager s3c4 530a 4- 52 nras ndwe address data mclko noe trp = 0 (1 cycle) tcs = 1 (2 cycles) tcp = 0 (1 cycle) trc = 0 (1 cycle) ncas tcp data trc column addr tndwe trp tnrasf row addr column addr (same page) tnrasr tncaswr tndwe tcs tcs taddrd data tncaswf figure 4-33. edo/fp dram bank write timing (page mode)
S3C4530A system man ager 4- 53 cke nsdcs addr mclko key nsdras nsdcas ba a10/ap ndwe dqm 200um precharge (all banks) auto refresh auto refresh mode register set (mrs) key rfu 0 a9 tm 0 0 a8 a7 cas latency 0 1 0 a6 a5 a4 bt 0 a3 burst length 0 0 0 a2 a1 a0 high level is necessary. figure 4-34. sdram power-up sequence
system manager s3c4 530a 4- 54 note 3 notes: 1. there is minimum 1 cycle gap between data-in and data-out of sdram to prevent bus confliction. 2. all dqm signals go to zero during read operation. 3. only valid signals go to zero during write operation. nsdcs addr mclko nsdras nsdcas ndwe data dqm 1 2 3 4 5 6 7 8 9 10 11 12 13 row precharge (all banks) row active read fetch write read fetch cke note 2 0x0 0xf 0xf 0x0 0xf wd rd rd col0 col2 col1 trp trcd note 1 figure 4-35. non-burst, read-write-read cycles @cas latency = 2, burst length = 1
S3C4530A system man ager 4- 55 mclko nsdcs nsdras nsdcas ndwe cke dqm 1 2 3 4 5 6 7 8 9 10 11 12 13 address data precharge (all banks) row active read row trcd trp col0 col1 col2 col3 rd2 rd0 rd3 rd1 0xf 0xf 0x0 fetch fetch fetch fetch figure 4-36. sdram burst-read
system manager s3c4 530a 4- 56 mclko nsdcs nsdras nsdcas ndwe cke dqm 1 2 3 4 5 6 7 8 9 10 11 12 13 address data precharge (all banks) row active row trcd trp col0 col1 col2 col3 d2 d1 d0 d3 0xf 0xf 0x0 write write write write figure 4-37. sdram burst-write
S3C4530A system man ager 4- 57 dram interface features the S3C4530A provides a fully programmable external dram interface. you can easily modify the characteristics of this interface by manipulating the corresponding dram control registers. programmable features include ? external data bus width ? control fast page or edo mode by dramcon[0] ? select fast page/edo mode or sdram mode by syscfg ? number of access cycles for each dram bank, and ? cas strobe time, cas pre-charge time, ras to cas delay, ras pre-charge time the refresh and external i/o control register, refextcon, controls dram refresh operations and external i/o bank accesses. the S3C4530A eliminates the need for an external refresh signal by automatically issuing an internal cas-before-ras refresh or auto-refresh control signal. the S3C4530A generates row and column addresses for dram accesses with 26-bit internal address bus. it also supports symmetric or asymmetric dram addressing by changing the number of column address lines from 8 to 11. edo mode dram accesses the timing for accessing a dram in edo mode is comparable to dram accesses in normal fast page mode. however, in edo mode, the S3C4530A cpu fetches data (when read) one-half clock later than in normal fast page mode. this is possible because edo mode can validate the data even if cas goes high when ras is low. in this way, gives the cpu sufficient time to access and latch the data so that the overall memory access cycle time can be reduced. synchronous dram accesses synchronous dram interface features are as follows: mrs cycle with address key program ? cas latency (2 cycles) ? burst length (1) ? burst type (sequential) auto refresh four word burst transfer for cache linefill, ethernet dma and hdlc dma operation. sdram interface signal: cke, sdclk, nsdcs[3:0], nsdcas, nsdras, dqm[3:0], addr[10]/ap the address bits except row and column address among the 23-bit internal address bus can be assigned to bank select address(ba) for sdram. see the sdram interface example, figure 4-38.
system manager s3c4 530a 4- 58 available samsung sdram components for S3C4530A components S3C4530A can support below sdram configuration for 1 bank. 2mbytes to 1 bank ? 1 (2mx32 with 4banks) 4mbytes to 1 bank ? 2 (1mx16 with 2banks) 8mbytes to 1 bank ? 4 (2mx8 with 2banks) 16mbytes to 1bank ? 2 (4mx16 with 2/4banks) 32mbytes to 1bank ? 4 (8mx8 with 2/4banks) you can select any combination among them. sdram components that are available are as follow. x4 sdram whose capacity is larger than 16m sdram is not supported at S3C4530A. 16m bit sdram ? 4mx4 with 2banks (supported) ra0?ra10, ca0?ca9 ? 2mx8 with 2banks (supported) ra0?ra10, ca0?ca8 ? 1mx16 with 2banks (supported) ra0?ra10, ca0?ca7 64m bit 2banks sdram ? 16mx4 with 2banks (not supported) ra0?ra12, ca0?ca9 ? 8mx8 with 2banks (supported) ra0?ra12, ca0?ca8 ? 4mx16 with 2banks (supported) ra0?ra12, ca0?ca7 64m bit 4banks sdram ? 16mx4 with 4banks (not supported) ra0?ra11, ca0?ca9 ? 8mx8 with 4banks (supported) ra0?ra11, ca0?ca8 ? 4mx16 with 4banks (supported) ra0?ra11, ca0?ca7 2mx32 (64m bit) sdram ? 2mx32 with 4banks (supported) ra0?ra10, ca0?ca7
S3C4530A system man ager 4- 59 100 pin dimm module sdram kmm330s104ct ? 1mx32 based on 2 1mx16 2banks components ra0?ra10, ca0?ca7 kmm330s204ct ? 2mx32 based on 4 1mx16 2banks components ra0?ra10, ca0?ca7 kmm330s2424ct ? 4mx32 based on 2 4mx16 4banks components ra0?ra11, ca0?ca7 kmm330s824ct ? 8mx32 based on 4 4mx16 4banks components ra0?ra11, ca0?ca7
system manager s3c4 530a 4- 60 relationship between can (column address number) and address mux output for sdram table 4-23. can and address mux output can output external address pins (addr) timing [21:15] 14 13 12 11 10 9 8 7-0 00 column address x a22 a21 a20 a19 a10/ap a9 a8 a7-a0 row address x a22 a21 a20 a19 a18 a17 a16 a15-a8 01 column address x 0 a22 a21 a20 a10/ap a9 a8 a7-a0 row address x 0 a22 a21 a20 a19 a18 a17 a16-a9 10 column address x 0 0 a22 a21 a10/ap a9 a8 a7-a0 row address x 0 0 a22 a21 a20 a19 a18 a17-a10 notes: 1. a22 to a0 depends on external bus width. in case of x32 memory, a[22:0] is word address. 2. a[22:0] consists of: bank address + valid row address + valid column address dram bank space the S3C4530A dram interface supports four dram banks. each bank can have a different configuration. you use the dram control registers, dramcon0-dramcon3, to program the dram access cycles and memory bank locations. each dram control register has two 10-bit address pointers, one base pointer and one next pointer, to denote the start and end address of each dram bank. the 10-bit pointer values are mapped to the address [25:16]. this gives each bank address an offset value of 64 k bytes (16 bits). the next pointer value will be the dram bank's end address + 1. system initialization values when the system is initialized, the four dram control registers are initialized to 00000000h, disabling all external drams.
S3C4530A system man ager 4- 61 S3C4530A clk d3 cs cke ras cas we addr dqm dq0-7 clk d2 cs cke ras cas we addr dqm dq0-7 clk d1 cs cke ras cas we addr dqm dq0-7 clk d0 cs cke ras cas we addr dqm dq0-7 mclko/sdclk nras/nsdcs 0,1,2,3 ncas2/cke ncas0/nsdras ncas1/nsdcas ndwe addr[10:0] nwbe[3:0]/dqm[3:0] xdata[31:0] addr[11] ba0 all sdram's ba pin <3> <2> <1> <0> figure 4-38. sdram application example (4 components have the following features: 1m 8bit 2banks 9bit column, 11bit-row address)
system manager s3c4 530a 4- 62 dram refresh and external i/o control register the S3C4530A dram interface supports the cas-before-ras (cbr) refresh mode for edo/fp dram and auto-refresh for sdram. settings in the dram refresh and external i/o control register, refextcon, control dram refresh mode, refresh timings, and refresh intervals. refextcon also contains the 10-bit base pointer value for the external i/o bank 0. note whenever the S3C4530A cpu writes one of system manager registers, the validity of special register field (that is, the vsf bit) is automatically cleared and the external bus is disabled. to reactivate external bus, you must set the vsf bit to "1" using a stmia instruction. it is recommended that programmers always use stmia instructions to write the 10 system manager special registers. the instruction used to set the vsf bit should always be the last instruction in the register write sequence.
S3C4530A system man ager 4- 63 [9:0] external i/o bank 0 base pointer (base address) this value is the start address of i/o external i/o bank 0. start address is defined as external i/o bank 0 base pointer << 20. the end address of external i/o bank 0 is defined as external i/o bank 0 base pointer >> 20 + 256 kbytes - 1. note: all external i/o banks are located in the continuous adress space which begins at the start address of external i/o bank 0. in case of pd_id value is 0x13, the size of each external i/o bank is fixed at 256kbytes. the start and end addresses of the other three external i/o banks can be derived from the external i/o bank 0 base pointer value. in case of pd_id value is 0x03, each bank's space is 16kbytes. and it's base pointer can be handled with 10bit. [15] validity of spedial register field (vsf) 0 = not accessible to memory bank 1 = accessible to memory bank [16] refresh enable (ren) 0 = disable dram refresh 1 = enable dram refresh [19:17] cas hold time (tchr) row cycle time (trc) (note 1) 000 = 1 cycle 001 = 2 cycles 010 = 3 cycles 011 = 4 cycles 100 = 5 cycles 101 = not used (6 cycles) 110 = not used 111 = not used [20] cas setup time (tcsr) (note 2) 0 = 1 cycle 1 = 2 cycles [31:21] refresh count value (duration) the refresh period is calculate as (211 - value + 1)/fmck notes: 1. in edo/normal dram mode, cas hold time can be programmed upto 5 cycles. but in sdram mode, this bit fields function are defined as row cycle time (trc) and can be programmed upto 6 cycles. 2. in sdram mode, this bit field is reserved. refresh count value tchr refextcon t c s r r e n v s f 0 0 0 0 0 external i/o bank 0 base pointer 31 20 19 10 9 0 21 17 16 15 14 13 12 11 4 3 figure 4-39. dram refresh and external i/o control register (refextcon)
system manager s3c4 530a 4- 64 continuous 256 kword address space for 4 external i/o banks 64 kwords (fixed for all i/o banks) external i/o bank 3 external i/o bank 2 external i/o bank 1 external i/o bank 0 end address of external i/o bank 0 start address of external i/o bank 0 start address of external i/o bank n = (external i/o bank 0 base pointer << 20) + 256 kbytes x n end address of external i/o bank n = (external i/o bank 0 base pointer << 20) + 256 kbytes x (n + 1) - 1 where, n is an external i/o bank number (= 0, 1, 2, 3) figure 4-40. external i/o bank address map
S3C4530A system man ager 4- 65 ndwe/ noe mclko ncas nras address data figure 4-41. edo/fp dram refresh timing
system manager s3c4 530a 4- 66 mclko ndwe cke nsdcs t rp precharge (all banks) auto refresh new command nsdras nsdcas t rc high level is necessary figure 4-42. auto refresh cycle of sdram note: at auto-refresh cycle, dram bank0's trp bit field is used as ras pre-charge time parameter.
S3C4530A unified instructio n/data cache 5- 1 5 unified instruction/data cache overview the S3C4530A cpu has a unified internal 8k byte instruction/data cache. using cache control register settings, you can use part or all of this cache as internal sram. to raise the cache hit ratio, the cache is configured using two-way, set-associative addressing. the replacement algorithm is pseudo-lru (least recently used). the cache line size is four words (16 bytes). when a miss occurs, four words must be fetched consecutively from external memory. typically, risc processors take advantage of unified instruction/data caches to improve performance. without an instruction cache, bottlenecks that occur during instruction fetches from external memory may seriously degrade performance. cache configuration the S3C4530A?s 4k byte, two-way set-associative instruction/data cache uses a 15-bit tag address for each set. the cs bits (a 2-bit value) in tag memory stores information for cache replacement. when a reset occurs, the cs value is "00", indicating that the contents of cache set 0 and cache set 1 are invalid. when the first cache fill operation occurs while exiting from the reset operation, the cs value becomes "01" at the specified line to indicate that only set 0 is valid. when the subsequent cache fill occurs, the cs value becomes "11" at the specified line, indicating that the contents of both set 0 and set 1 are valid.
unified instruction/data cache s3c45 30a 5- 2 switch cs set 1 tag set 0 tag 15 (14) 2 tag ram (32-bit) set 1 icache line = 4 instruction/data (128-bit) set 0 icache line = 4 instruction/data (128-bit) decoder 6-bit 2-bit height = 128 (256) 7 (8)-bit height = 128 (256) 32 2 (set 0 hit) (set 1 hit) 15 enable non-cacheable control 15 (14) 2 32 32 instr3 instr2 instr1 instr0 32-bit instr3 instr2 instr1 instr0 32-bit 7 (8)-bit 31 27 28 tag address (15-bit) 25 0 30 29 26 10 9 4 3 2 1 24 23 bit 28 24 23 1 0 0 1 0 1 1 1 0 set 0 direct access set 1 direct access tag direct access figure 5-1. memory configuration for 4-kbyte (or 8-kbyte) cache
S3C4530A unified instructio n/data cache 5- 3 cache replace operations when the contents of two sets are valid and when the content of the cache must be replaced due to a cache miss, the cs value becomes "10" at specified line. this indicates that the content of set 0 (s0) was replaced. when cs is "10" and when another replacement is required due to a cache miss, the content of set 1 (s1) is replaced by changing the cs value to "01". to summarise , at its normal steady state, the cs value is changed from "01" or "10" to "10" or "01". this modification provides the information necessary to implement a 2-bit pseudo-lru (least recently used) cache replacement policy. s0 only: 01 miss hit ; set 0, set 1 all invalid ; chahe miss occurs ; set 0 = valid, set 1 = invalid status does not change on hit ; read miss ; av_s1d = all valid and set 1 is dirty. dirty means to access just before; status does not change on hit. ; av_s0d = all valid and set 0 is dirty. miss av-s0d: 10 av-s1d: 11 hit 1 hit 0 miss or hit 1 miss or hit 0 reset(/) nvalid: 00 figure 5-2. cache replace algorithm state diagram
unified instruction/data cache s3c45 30a 5- 4 cache disable/enable to disable the cache disable entirely following a system reset, you must set syscfg[1] to "0". by setting the cache mode bits, syscfg[5:4], you can specify a cache size of 0, 4, or 8k bytes. if you do not need the entire 8- kbyte area for cache, you can use the remaining area as normal internal sram. the start address of the internal sram area is defined by writing an appropriate value to syscfg[15:6]. cache flush operation to flush cache lines, you must write a zero to tag memory bits 31 and 30, respectively. the 4-kbyte set 0 ram area, 4-kbyte set 1 ram area, and the 1-kbyte tag ram area (total 256 words) can be accessed from locations 0x10000000h, 0x10800000h, and 0x11000000h, respectively. you can do this independently of the current cache mode bit and cache enable bit settings. tag ram is normally cleared by hardware following a power-on reset. however, if you change the cache or memory bank configuration when the cache is being enabled, you will have to clear the tag ram area using application software. non-cacheable area control bit although the cache affects the entire system memory, it is sometimes necessary to define non-cacheable areas when the consistency of data stored in memory and the cache must be ensured. to support this, the S3C4530A provides a non-cacheable area control bit in the address field, addr[26]. if addr[26] in the rom/sram, flash memory, dram, or external i/o bank's access address is "0", then the accessed data is cacheable. if the addr[26] value is "1", the accessed data is non-cacheable. cacheable area non-cacheable area cacheable area 002_0000 3ff_ffff 000_ffff 000_0000 000_0000 cacheable area 400_0000 401_0000 401_ffff 3ff_ffff 7ff_ffff note: the non-cacheable area has the same space in memory as t he cacheable a rea. to access the non-cacheable area, you can change the address of the space in memory using non-cacheable control bit . 16 m word non-cacheable area figure 5-3. non-cacheable area control note a swap command must be used within a non-cacheable area.
S3C4530A i 2 c bus controller 6- 1 6 i 2 c bus controller overview the S3C4530A's internal ic bus (i 2 c-bus) controller has the following important features: ? it requires only two bus lines, a serial data line (sda) and a serial clock line (scl). when the i 2 c-bus is free, both lines are high level. ? each device that is connected to the bus is software-addressable by a single master using a unique address. slave relationships on the bus are constant. the bus master can be either a master-transmitter or a master- receiver. the i 2 c bus controller supports only single master mode. ? it supports 8-bit, bi-directional, serial data transfers. ? the number of ics that you can connect to the same i 2 c-bus is limited only by the maximum bus capacitance of 400 pf. figure 6-1 shows a block diagram of the S3C4530A i 2 c-bus controller data control scl control 0 serial clock prescaler control status register (iiccon) 0 busy cond1 cond0 ack lrb ien prescaler register (iicps) system clock (fmck) 16 scl sda bf shift buffer register (iicbuf) figure 6-1. i 2 c bus block diagram
i 2 c bus controller S3C4530A 6- 2 functional description the S3C4530A i 2 c bus controller is the master of the serial i 2 c-bus. using a prescaler register, you can program the serial clock frequency that is supplied to the i 2 c bus controller. the serial clock frequency is calculated as follows: mclk / (16 (prescaler register value + 1) + 3) to initialize the serial i 2 c-bus, the programmer sends a start code by writing "01" to bits [5:4]of the control status register, iiccon. the bus controller then sends the 7-bit slave address and a read/write control bit through shift buffer register. the receiver sends an acknowledge by pulling the sda line from high to low during a master scl pulse. to continue the data write operation, you must set the bf bit in the control status register and then write the data to the shift buffer register. whenever the shift buffer register is read or written, the bf bit is cleared automatically. for the consecutive read/write operations, you must set the ack bit in the control status register. for read operations, you can read the data after you have set the bf bit in the control status register. to signal the end of the read operation, you can reset the ack bit to inform the receiver/transmitter when the last byte is to be written/read. following a read/write operation, you set iiccon[5:4] to "10" to generate a stop code. if you want to complete another data transfer before issuing the stop code, you can send the start code using the repeat start command (with iiccon[5:4] = "11"). when the slave address and read/write control bit have been sent, and when the receive acknowledge has been issued to control scl timing, the data transfer is initiated.
S3C4530A i 2 c bus controller 6- 3 i 2 c-bus concepts basic operation the i 2 c-bus has two wires, a serial data line (sdl) and a serial clock line (scl), to carry information between the ics connected to the bus. each ic is recognized by a unique address and can operate as either a transmitter or receiver, depending on the function of the specific ics. the i 2 c-bus is a multi-master bus. this means that more than one ic which is capable of controlling the bus can be connected to it. data transfers proceed as follows: case 1: a master ic wants to send data to another ic (slave): 1. master addresses slave 2. master sends data to the slave (master is transmitter, slave is receiver) 3. master terminates the data transfer case 2: a master ic wants to receive information from another ic (slave): 1. master addresses slave 2. master receives data from the slave (master is receiver, slave is transmitter) 3. master terminates the data transfer even in case 2, the master ic must generate the timing signals and terminate the data transfer. if two or more masters try to put information simultaneously onto the bus, the first master to issue a "1" when the other issues a "0" will lose the bus arbitration. the clock signals used for arbitration are a synchronized combination of the clocks generated by the bus masters using the wired-and connection to the scl line. the master ic is always responsible for generating the clock signals on the i 2 c-bus. bus clock signals from a master can only be altered by 1) a slow slave ic which "stretches" the signal by temporarily holding the clock line low, or 2) by another master ic during arbitration. general characteristics both sda and scl are bi-directional lines which are connected to a positive supply voltage through a pull-up resistor. when the i 2 c-bus is free, the sda and scl lines are both high level. the output stages of i 2 c interfaces connected to the bus have an open-drain or open-collector to perform the wired-and function. data on the i 2 c- bus can be transferred at a rate up to 100 kbits/s. the number of interfaces that can be connected to the bus is solely dependent on the limiting bus capacitance of 400 pf. bit transfers due to the variety of different ics (cmos, nmos, and i2l, for example) which can be connected to the i 2 c-bus, the levels of logic zero (low) and logic one (high) are not fixed and depend on the associated level of v dd . one clock pulse is generated for each data bit that is transferred.
i 2 c bus controller S3C4530A 6- 4 data validity the data on the sda line must be stable during the high period of the clock. the high or low state of the data line can only change when clock signal on the scl line is low. start and stop conditions start and stop conditions are always generated by the master. the bus is considered to be busy after the start condition is generated. the bus is considered to be free again when a brief time interval has elapsed following the stop condition. ? start condition: a high-to-low transition of the sda line while scl is high. ? stop condition: a low-to-high transition of the sda line while scl is high. start condition address p 9 stop condition sda scl 1-7 8 9 1-7 8 9 1-7 8 r/w ack data ack data ack s figure 6-2. start and stop conditions
S3C4530A i 2 c bus controller 6- 5 data trsansfer operations data byte format every data byte that is put on the sda line must be 8 bits long. the number of bytes that can be transmitted per transfer is unlimited. each byte must be followed by an acknowledge bit. data is transferred msb-first. if the receiver cannot receive another complete byte of data until it has performed some other function (such as servicing an internal interrupt), it can hold the clock line scl low to force the transmitter into a wait state. the data transfer then continues when the receiver is ready for another byte of data and releases the scl line. acknowledge procedure data transfer with acknowledge is obligatory. the acknowledge-related clock pulses must be generated by the bus master. the transmitter releases the sda line (high) during the acknowledge clock pulse. the receiver must pull down the sda line during the acknowledge pulse so that it remains stable low during the high period of this clock pulse. usually, a receiver which has been addressed is obliged to generate an acknowledge after each byte is received. when a slave receiver does not acknowledge from the slave address, the slave must leave the data line high. the master can then generate a stop condition to abort the transfer. if a slave receiver acknowledges the slave address, but later in the transfer cannot receive any more data bytes, the master must again abort the transfer. this is indicated by the slave not generating the acknowledge on the first byte to follow. the slave leaves the data line high and the master generates the stop condition. if a master receiver is involved in a transfer, it must signal the end of data to the slave transmitter by not generating an acknowledge on the last byte that was clocked out of the slave. the slave transmitter must then release the data line to let the master generate the stop condition.
i 2 c bus controller S3C4530A 6- 6 data transfer format data transfers uses the format shown in figure 6-3. after the start condition has been generated, a 7-bit slave address is sent. the eighth bit is a data direction bit (r/w). a "0" direction bit indicates a transmission (write) and a "1" indicates a request for data (read). a data transfer is always terminated by a stop condition which is generated by the master. however, if a master still wishes to communicate on the bus, it can generate another start condition and address another slave without first generating a stop condition. this feature supports the use of various combinations of read/write formats for data transfers. s slave address w a data 1 (8 bits) a data 2 data m a a p s slave address r a data 1 (8 bits) a data 2 data m a a p multiple byte slave receiver format: multiple byte slave transmitter format: note: s (start) w (write; bit value is 0) r (read; bit value is 1) p (stop), a (acknowledge; the ack is first sent to the slave. afterwards, the direction depends on the data transfer direction. in other words, if the mater reads the data, it sends the ack.) figure 6-3. data transfer format
S3C4530A i 2 c bus controller 6- 7 i 2 c-bus addressing the addressing procedure for the i 2 c-bus is such that the first byte after the start condition determines which slave the master will select. usually, this first byte immediately follows the start procedure. an exception is the "general call" address which can address all ics simultaneously. when this address is used, all ics should, in theory, respond with an acknowledge. however, ics can also be made to ignore this address. the second byte of the general call address then defines the action to be taken. definition of bits in the first data byte the first seven bits of the first data byte make up the slave address. the eighth bit is the lsb, or direction bit, which determines the direction (r/w) of the message. when an address is sent, each ic on the bus compares the first 7 bits received following start condition with its own address. if the addresses match, the ic considers itself addressed by the master as a slave receiver or a slave transmitter. general call address the general call address can be used to address every ic that connected to the i 2 c-bus. however, if an ic does not need any of the data supplied within the general call structure, it can ignore this address by not acknowledging it. if an ic does require data from a general call address, it can then acknowledge this address and behave as a slave receiver. the second and following bytes will be acknowledged by every slave receiver capable of handling this data. a slave which cannot process one of these bytes must ignore it by not acknowledging. the meaning of the general call address is always specified in the second byte. start byte every data transfer is preceded by a start procedure: ? a start condition, s ? a start byte, "00000001" ? an acknowledge (ack) clock pulse, and ? a repeated start condition, sr after the start condition (s) has been transmitted by a master which requires bus access, the start byte ("00000001") is transmitted. another ic can therefore sample the sda line at a low sampling rate until one of the seven zeros in the start byte is detected. after it detects this low level on the sda line, the ic can switch to a higher sampling rate to find the repeated start condition (sr) which is then used for synchronization. (a) hardware receiver will reset upon receipt of the repeated start condition (sr) and will therefore ignore the start byte.) an acknowledge-related clock pulse is generated after the start byte. this is done only to conform with the byte handling format used on the bus. no ic is allowed to acknowledge the start byte.
i 2 c bus controller S3C4530A 6- 8 i 2 c bus special registers the i 2 c-bus controller has three special registers: a control status register (iiccon), a prescaler register (iicps), and a shift buffer register (iicbuf). control status register (iiccon) the control status register for the i 2 c-bus, iiccon, is described in table 6-2. table 6-1. control status register (iiccon) register offset address r/w description rest value iiccon 0xf000 r/w control status register 0x00000000 table 6-2. iiccon register description bit number bit name description [0] buffer flag (bf) the bf bit is set when the buffer is empty in transmit mode or when the buffer is full in receive mode. to clear the buffer, you write a "0" to this bit. the bf bit is cleared automatically whenever the iicbuf register is written or read. if you set bf bit to one, the i 2 c -bus is stopped. to activate i 2 c-bus, you should clear the bf bit to zero. [1] interrupt enable (ien) setting the interrupt enable bit to "1" enables the i 2 c-bus interrupt. [2] last received bit (lrb) the lrb bit is read only. it holds the value of the last received bit over the i 2 c-bus. normally, this bit will be the value of the slave acknowledgement. to check for slave acknowledgement, you test the lrb. [3] acknowledge enable (ack) the ack bit is normally set to "1". this causes the i 2 c-bus controller to send an acknowledge automatically after each byte. this bit must be "0" when the i 2 c-bus controller is operating in receiver mode and requires no further data to be received from the slave transmitter. this causes a negative acknowledge on the i 2 c-bus, which halts further reception from the slave device. [5:4] cond1, cond0 these bits control the generation of the start, stop, and repeat start conditions: "00" = no effect, "01" = start, "10" = stop, and "11" = repeat start. [6] bus busy (busy) this bit is a read-only flag that indicates when the i 2 c-bus is in use. a "1" indicates that the bus is busy. this bit is set or cleared by a start or stop condition, respectively. [7] reset if "1" is written to the reset bit, the i 2 c-bus controller is reset to its initial state. [31:8] reserved not applicable.
S3C4530A i 2 c bus controller 6- 9 [0] buffer flag (bf) 0 = automatically cleared when the iicbuf register is written or read. to manually clear the bf, write 0. 1 = automatically set when the buffer is empty in transmit mode or when the buffer is full in receive mode. [1] interrupt enable (ien) 0 = disable 1 = enable; an interrupt is generated if the bf bit is 1. [2] last received bit (lrb) use this read-only status bit to theck for ack signals from the receiver (slave), or to monitor sda operation of sda when writing 11 to iiccon [5:4] for repeated starts. 0 = the most recent sda is low. (ack is received) 1 = the most recent sda is high. (ack not received) [3] acknowledge enable (ack) controls generation of an ack signal in receive mode. 0 = do not generate an ack at 9th scl (no more received data is required from the slave) 1 = generate an ack signal at 9th scl. [5:4] cond 1 and cond 0 generate a bus control such as start or stop. 00 = no effect. 01 = generate start condition. 10 = generate stop condition. 11 = scl will be released to high level to generate repeated start condition. [6] bus busy (busy) data transmission is in progress on the iic-bus. 0 = bus is currently not in use. (not busy) 1 = bus is in use. (busy) [7] reset 0 = normal 1 = reset the iic-bus controller. [31:8] reserved b f i e n l r b a c k c o n d 0 c o n d 1 b u s y r e s e t reserved 31 8 7 0 9 6 5 4 3 2 1 figure 6-4. i 2 c control status register
i 2 c bus controller S3C4530A 6- 10 shift buffer register (iicbuf) the shift buffer register for the i2c-bus described in table 6-4. table 6-3. iicbuf register register offset address r/w description rest value iicbuf 0xf004 r/w shift buffer register undefined table 6-4. iicbuf register description bit number bit name description [7:0] data this data field acts as serial shift register and read buffer for interfacing to the i 2 c-bus. all read and write operations to/from the i 2 c-bus are done via this register. the iicbuf register is a combination of a shift register and a data buffer. 8-bit parallel data is always written to the shift register, and read form the data buffer. i 2 c- bus data is always shifted in or out of the shift register. [31:8] reserved not applicable. prescaler register (iicps) the prescaler register for the i 2 c-bus is described in table 6-6. table 6-5. iicps register register offset address r/w description rest value iicps 0xf008 r/w prescaler register 0x00000000 table 6-6. iicps register description bit number bit name description [15:0] prescaler value this prescaler value is used to generate the serial i 2 c-bus clock. the system clock is divided by (16 x (prescaler value + 1) + 3) to make the serial i 2 c clock. if the prescaler value is zero, the system clock is when divided by 19 to make the serial i 2 c clock. [31:16] reserved not applicable.
S3C4530A i 2 c bus controller 6- 11 prescaler counter register (iiccnt) the prescaler counter register for the i 2 c-bus is described in table 6-8. table 6-7. iiccnt register register offset address r/w description rest value iiccnt 0xf00c r/w prescaler counter register 0x00000000 table 6-8. iiccnt register description bit number bit name description [15:0] counter value this 16-bit value is the value of the prescaler counter. it is read (in test mode only) to check the counter?s current value. [31:16] reserved not applicable.
i 2 c bus controller S3C4530A 6- 12 notes
S3C4530A ethernet c ontroller 7- 1 7 ethernet controller overview the S3C4530A has an ethernet controller which operates at either 100-mbits or 10-mbits per second in half- duplex or full-duplex mode. in half-duplex mode, the controller supports the ieee 802.3 carrier sense multiple access with collision detection (csma/cd) protocol. in full-duplex mode, it supports the ieee 802.3 mac control layer, including the pause operation for flow control. the ethernet controller s mac layer supports both the media independent interface (mii) and the buffered dma interface (bdi). the mac layer itself consists of the receive and the transmit blocks, a flow control block, a content addressable memory (cam) for storing network addresses, and a number of command, status, and error counter registers. the mii supplies the transmit and receive clocks of 25 mhz for 100-mbit/s operation or 2.5 mhz at the 10-mbit/s speed. the mii conforms to the iso/iec 802-3 standards for a media-independent layer which separates physical layer issues from the mac layer.
ethernet controller S3C4530A 7- 2 s y s t e m b u s b d i m i i / 10 m b p s 7 - w i r e bdma tx buffer controller bdma tx buffer (64 words) bus arbiter/ controller bdma rx buffer (64 words) bdma rx buffer controller cam contents memory (32-words) mac address cam interface and comparator mac control and status register bdma+sbus i/f 32 32 32 physical layer bdma control and status register station manager 32 32 32 8 8 mac tx buffer (80 bytes) mac rx buffer (16 bytes) preamble/ jam/pad/crc generator mac tx buffer controller mac rx buffer controller flow controller crc checker m d i figure 7-1. ethernet system flow control
S3C4530A ethernet c ontroller 7- 3 features and benefits the most important features and benefits of the S3C4530A ethernet controller are as follows: ? cost-effective connection to an external r ic/ethernet backbone ? buffered dma (bdma) engine using burst mode ? bdma tx/rx buffers (256 bytes/256 bytes) ? mac tx/rx fifos (80 bytes/16 bytes) to support re-transmit after collision without dma request and to handle dma latency ? data alignment logic ? endian translation ? support for old and new media (compatible with existing 10-mbit/s networks) ? 100-mbit/s or 10-mbits/s operation to increase price/performance options and to support phased conversions ? full ieee 802.3 compatibility for existing app lications ? media independent interface (mii) or 7-wire interface ? station management (sta) signaling for external physical layer configuration and link negotiation ? on-chip cam (21 addresses) ? full-duplex mode for doubled bandwidth ? pause operation hardware support for full-duplex flow control ? long packet mode for specialized environments ? short packet mode for fast testing ? pad generation for ease of processing and reduced processing time
ethernet controller S3C4530A 7- 4 mac function blocks the major function blocks of the ethernet controller s mac layer are described in table 7-1 and figure 7-1. table 7-1. mac function block descriptions function block description media independent interface (mii) the interface between the physical layer and the transmit and receive blocks. transmit block moves the outgoing data from the transmit buffer to the mii. the transmit block includes circuits for generating the crc, checking parity, and generating preamble or jam. the transmit block also has timers for back-off after collision and for the interframe gap the follows a transmission. receive block accepts incoming data from the mii and stores it in the receive fifo. the receive block has logic for computing and checking the crc value, generating parity for data from the mii, and checking minimum and maximum packet lengths. the receive block also has a content addressable memory (cam) block which provides for address lookup, and for acceptance or rejection for packets based on their destination address. flow control block recognizes mac control packets and supports the pause operation for full-duplex links. the flow control block also supports generation of pause packets, and provides timers and counters for pause control. mac control (command) and status registers controls programmable options, including the enabling or disabling of signals which notify the system when conditions occur. the status registers hold information for error handling software, and the error counters accumulate statistical information for network management software. loop-back circuit provides for mac-layer testing in isolation from the mii and physical layer.
S3C4530A ethernet c ontroller 7- 5 b d i tx_db[7:9] backoff and intergap timer parity check transmit block mac loop-back 10 m b / s i/f txd_10 flow control crc and cam filter mac control and status register mii station manager m i i rxd_10 txd[3:0] rxd[3:0] mdc rx_db[7:0] mac receive fifo (16 bytes) parity generator mac transmit fifo (80 bytes) receive block mdio preamble and jam generator pad and crc generator figure 7-2. mac layer flow control function blocks
ethernet controller S3C4530A 7- 6 media independent interface (mii) transmit and receive blocks both operate using the mii, which was developed by the ieee802.3 task force on 100-mbit/s ethernet. this interface has the following characteristics: ? media independence ? multi-vendor points of interoperability ? supports connection of mac layer and physical layer entity (phy) devices ? capable of supporting both 100-mbit/s and 10-mbit/s data rates ? data and delimiters are synchronous to clock references ? provides independent 4-bit wide transmit and receive data paths ? uses ttl signal levels that are compatible with common digital cmos asic processes ? supports connection of phy layer and station management (sta) devices ? provides a simple management interface ? capable of driving a limited length of shielded cable physical layer entity (phy) the physical layer entity, or phy, performs all of the decoding/encoding on incoming and outgoing data. the manner of decoding and encoding (manchester for 10base-t, 4b/5b for 100base-x, or 8b/6t for 100base-t4) does not affect the mii. the mii provides the raw data it receives, starting with the preamble and ending with the crc. the mii expects raw data for transmission, also starting with the preamble and ending with the crc. the mac layer also generates jam data and transmits it to the phy. buffered dma interface (bdi) the buffered dma interface (bdi) supports read and write operations across the system bus. two eight-bit buses transfer data with optional parity checking. the system interface initiates data transfers. the mac-layer controller responds with a ready signal to accept data for transmission, or to deliver data which has been received. an end- of-frame signal indicates the boundary between packets.
S3C4530A ethernet c ontroller 7- 7 the mac transmit block the mac transmit block is responsible for transmitting data. it complies with the ieee802.3 standard for carrier sense multiple access with collision detection (csma/cd) protocol. the mac transmit block consists of the following sections: ? transmit fifo and controllers ? preamble and jam generators ? pad generator ? parallel crc generator ? threshold logic and counters ? back-off and retransmit timers ? transmit state machine figure 7-3 shows the mac transmit function blocks in detail. tx_db [7:0] and parity write fifo controller and counter threshold logic and counters sys_clk domain mac transmit fifo (80 x 9) parity check preamble and jam generator transmit state matchine tx_clk domain 9 9 8 txd [3:0] crs tx_er tx_en col tx_clk m i i a n d 10 m b y t e i/f b d i read fifo controller and counter back off and retransmit timers tx_eof tx_wr# tx_rdy pad generator crc generator figure 7-3. mac transmit function blocks
ethernet controller S3C4530A 7- 8 transmit fifo and read/write controllers the transmit fifo has an 80-byte depth. an extra bit is associated with each data byte for parity checking. this 80 -byte by 9-bit size allows the first 64 bytes of a data packet to be stored and retransmitted, without further system involvement, in case of a collision. if no collision occurs and transmission is underway, the additional 16 bytes handle system latency and avoid fifo under-run. when the system interface has set the transmit enable bit in the appropriate control register, the transmit state machine requests data from the bdi. the system controller then fetches data from the system memory. the fifo controller stores data in the transmit fifo until the threshold for transmit data is satisfied. the fifo controller passes a handshaking signal to the transmit state machine, indicating that sufficient data is in the fifo to start the transmit operation. if the fifo is not full, the fifo controller issues a request to the bdi for more data. the transmit state machine continues transmitting data until it detects the end-of-frame signal, which signals the last byte. it then appends the calculated crc to the end of the data (unless the crc truncate bit in the transmit control register is set). the packet transmit bit in the status register is set, generating an interrupt if it is enabled. the fifo counters in this block (the write counter) and the transmit fifo counter of the transmit state machine (the read counter) co-ordinate their functions based on each other's count value, although they do have different clock sources. the fifo controller stores parity bits with the data in the fifo. it checks for parity and can halt transmission after reading the data out of the fifo and sending it for the crc calculation. if a parity error occurs, the fifo controller sets an error status bit, generating an interrupt if it is enabled. preamble and jam generator as soon as the transmit enable bit in the control register is set and there are eight bytes of data in the fifo, the transmit state machine starts the transmission by asserting the tx_en signal and transmitting the preamble and the start frame delimiter (sfd). in case there is a collision, it transmits a 32-bit string of "1s" after the preamble as a jam pattern. pad generator if a short data packet is transmitted, the mac will normally generate pad bytes to extend the packet to a minimum of 64 bytes. the pad bytes consist entirely of "0" bits. a control bit is also used to suppress the generation of pad bytes. parallel crc generator the crc generation of the outgoing data starts from the destination address and continues through the data field. you can suppress crc generation by setting the appropriate bit in the transmit control register. this is useful in testing, for example, to force the transmission of a bad crc in order to test error detection in the receiver. it can also be useful in certain bridge or switch applications, where end-to-end crc checking is desired.
S3C4530A ethernet c ontroller 7- 9 threshold logic and counters the transmit state machine uses a counter and logic to control the threshold of when transmission can begin. before it attempts to initiate transmission, the mac waits until eight bytes or a complete packet has been placed in the transmit fifo. this gives the dma engine some latency without causing an underflow during transmission. back-off and retransmit timers when a collision is detected on the network, the transmitter block stops the transmission and starts a jamming pattern to ensure that all the nodes detect the collision. after this, the transmitter waits for a minimum of 96 bit times and then retransmits the data. after 16 attempts, the transmit state machine sets an error bit and generates an interrupt, if enabled, to signify the failure to transmit a packet due to excessive collisions. it flushes the fifo, and the mac is ready for the next packet. transmit data parity checker data in the fifo is odd-parity protected. when data is read for transmission, the transmit state machine checks the parity. if a parity error is detected, the transmit data parity checker does the following: ? it stops transmission. ? it sets the parity error bit in the transmit status register. ? it generates an interrupt, if enabled. transmit state machine the transmit state machine is the central control logic for the transmit block. it controls the passing of signals, the timers, and the posting of errors in the status registers.
ethernet controller S3C4530A 7- 10 the mac receive block the mac receive block is responsible for receiving data. it complies with the ieee802.3 standard for carrier sense multiple access with collision detection (csma/cd) protocol. after it receives a packet, the receive block checks for a number of error conditions: crc errors, alignment errors, and length errors. several of these checks can be disabled by setting bits in the appropriate control registers. depending on the cam status, the destination address and the receive block may reject an otherwise acceptable packet. the mac receive block consists of the following units: ? receive fifo, fifo controller, and cou nters ? receive bdi state machine ? threshold logic and counters ? cam block for address recognition ? parallel crc checker ? receive state machine the main components of the receive block are shown in figure 7-4. rx_db [7:0] and parity 9 mac receive fifo (16x10) cam checker crc checker receive bdi state machine rx_rd rx_rdy rx_eof rx_keep rx_toss rx_load cam_hit# read address sys_clk domain rx_clk domain write address /we receive state machine parity check rxd[3:0] rx_dv rx_er rx_clk bdi mii and 7-wire i/f write fifo controller and counter thershold logic and counter write fifo controller and counter sfd detect figure 7-4. mac receive function blocks
S3C4530A ethernet c ontroller 7- 11 receive fifo controller the receive fifo controller accepts data one byte at a time. parity starts with the destination address. the receive controller updates the counter with the number of bytes received. as the fifo stores the data, the cam block checks the destination address against its stored address. if the cam recognizes the address, the fifo continues receiving the packet. if the cam block does not recognize the address and rejects the packet, the receive block discards the packet and flushes the fifo. address cam and address recognition the cam block provides direct comparison address recognition. the cam compares the destination address of the received packet to stored addresses. if it finds a match, the receive state machine continues to receive the packet. the cam is organized to hold six-byte address entries. with its 32-word size, the cam can store 21 address entries. cam address entries 0, 1, and 18 are used to send the pause control packet. to send a pause control packet, you must write the destination address to cam0, the source address to cam1, and length/type, op-code, and operand to the cam18 entry. you must them write the mac transmit control register to set the send pause control bit. in addition, cam19 and cam20 can be used to construct a user-define control frame. parallel crc checker the receive block computes a crc across the data and the transmitted crc, and then checks that the resulting syndrome is valid. a parallel crc checking scheme handles data arriving in 4-bit nibbles at 100 mbps. to support full-duplex operation, the receive and transmit blocks have independent crc circuits. receive state machine in mii mode, the receive block receives data from the mii on the rxd[3:0] lines. this data is synchronized to rx_clk at 25 mhz or 2.5 mhz. in 7-wire mode, and at 10 mhz, data is received on the rxd_10 line only. after it detects the preamble and sfd, the receive state machine arranges data in byte configurations, generates parity, and stores the result in the receive fifo one byte at a time. if the cam block accepts the destination address, the receive fifo stores the rest of the packet. at the end of the reception, the receive block marks the packet received by setting the appropriate bits in the receive status register. any error in reception will reset the fifo and the state machine will wait for the end of the current packet. it will then idle while it is waiting for the next preamble and sfd. bdma interface receive state machine the bdma i/f receive state machine issues the rx_rdy signal to request that the receive fifo have data whenever data is present in the receive fifo. the last byte of the packet is signaled by asserting the rx_eof. in case there are any errors during the reception, or if there is a crc error at the end, the bdma i/f receive state machine asserts the rx_toss signal to indicate that the received packet should be discarded.
ethernet controller S3C4530A 7- 12 flow control block the flow control block provides for the following functions: ? recognition of mac control frames received by the receive block ? transmission of mac control frames, even if transmitter is paused ? timers and counters for pause operation ? command and status register (csr) interface ? options for passing mac control frames through to software d rivers the receive logic in the flow control block recognizes a mac control frame as follows: ? the length/type field must have the special value specified for mac control frames. the destination address must be recognized by the cam. the frame length must be 64 bytes, including crc. the crc must be valid, and the frame must contain a valid pause op-code and operation. ? if the length/type field does not have the special value specified for mac control frames, the mac takes no action, and the packet is treated as a normal packet. if the cam does not recognize the destination address, the mac rejects the packet. if the packet length is not 64 bytes, including crc, the mac does not perform the operation. the packet is then marked as a mac control packet, and is passed forward to the software drivers, if pass-through is enabled. you can set control bits in the transmit status register to generate a full-duplex pause operation or other mac control functions, even if the transmitter itself is paused. two timers and two corresponding csr registers are used during a pause operation. one timer/register pair is used when a received packet causes the transmitter to pause. the other pair is used to approximate the pause status of the other end of the link, after the transmitter sends a pause command. the command and status register (csr) interface provides control and status bits within the transmit and receive control registers and status registers. these lets you initiate the sending of a mac control frame, enable and disable mac control functions, and read the values of the flow control counters. control bits are provided for processing mac control frames entirely within the controller, or for passing mac control frames on to the software drivers. this lets you enable flow control by default even on software drivers which are not otherwise "flow control aware".
S3C4530A ethernet c ontroller 7- 13 buffered dma interface buffered dma (bdma) control blocks the bdma engine controls a transmit buffer and a receive buffer. the bdma transmit buffer holds data and status information for packets being transmitted. the bdma receive buffer holds data and status information for packets being received. each fifo has a control block which controls data being placed in, and removed from, the buffers. s y s t e m b u s i/f bus arbiter tx_underflow nreq_tx nreq_rx tx control machine b d i b d m a i/f tx_clk tx_wr tx_rdy half_full tx_db[7:0] sd [31:0] ( ( half_empty half_full - head ptr tail ptr bdma tx buffer (32 x 64) rx bus request address generator target address for rx source address for tx rx bus request rx_over flow data swapper big/little bdma rx buffer (33 x 64) - rx_widget rx control machine rx_db[7:0] half_empty rx_rdy rx_clk rx_rd sa[25:0] byte-to-word converter head ptr tail ptr nack nreq sd[31:0] word-to-byte converter tx widget big/little figure 7-5. bdma control blocks
ethernet controller S3C4530A 7- 14 the bus arbiter the bus arbiter decides which of the bdma buffer controllers, transmit (tx) or receive (rx), has the highest priority for accessing the system bus. the prioritization is dynamic. the bdma arbiter outputs a bus request signal (nreq) to the system manager when ? a buffer contains more words than the rx burst size, ? an eof (end of frame) was saved to the buffer, or ? a buffer contains more free space than the tx burst size. after it receives a bus acknowledge signal (nack) from the system manager, the bdma bus arbiter determines the correct bus access priority. if nreq_tx and nreq_rx were requested simultaneously, the bus arbiter decodes the nack signal using the following method: switch (half_empty, half_full) { case 2'b01: nack_rx ? nack case 2'b10: nack_tx ? nack default: //case 2'b00 or 2'b11: if (rx buffsize (head - tail) < tx buffsize) // rx more urgent nack_rx ? nack else nack_tx ? ? nack}
S3C4530A ethernet c ontroller 7- 15 bdma bus control logic the function blocks of the bdma controller provide logic for controlling bus master read and write operations across the system bus. this control logic supports the following operations: ? burst size control, to optimize system bus utilization. ? transmit threshold control (based on 1/8 of transmit buffer size) to match transmission latency to system bus latency. ? little-endian byte swapping, to support the data transfer of little-endian memory usage for frame data. ? a transmit/receive alignment widget to circumvent word alignment restricti ons. in systems with an atm lan emulation or an mpoa interface, and in certain other systems as well, the beginning of a packet should be placed on a byte or half-word boundary. you may not, however misalign the bdma transfer, as this would complicate the design of the dma, and would degrade performance. to avoid this, you can use an alignment widget between the bdma buffer (word) and the mac fifo (byte). in the receiver, the bdma bus control logic inserts a programmable number of bytes (up to three) into the received data stream while the preamble is being received. this adds some padding to the beginning of the frame. this padding can then be used to solve alignment problems downstream, without having to use a copy of the buffer. because there is never more than three bytes, this feature does not degrade performance. also, because the data is inserted prior to the concatenation of bytes into words, it does not misalign the subsequent dma transfer. the length of the alignment data is read from a control register. this length value should be set by software immediately after the mac module is reset, and it should not be modified. you can use a corresponding transmit alignment widget to remove data from the buffer. in the simplest implementation, the widget discards the first "n" bytes (up to three), where "n" is the value read from the transmit frame descriptor which configures the transmit alignment widget. memory data structures the flow control 100-/10-mbit/s ethernet controller uses three data structures to exchange control information and data: ? transmit frame descriptor ? receive frame descriptor ? frame data buffer each frame descriptor has the following elements: ? frame start address ? ownership bit ? control field for transmitter ? status field ? frame length ? next frame descriptor pointer figure 7-6 shows data structures of the transmit and receive frame descriptors.
ethernet controller S3C4530A 7- 16 data frames the ownership bit in the msb of the frame start address controls the owner of the descriptor. when the ownership bit is "1", the bdma controller owns the descriptor. when this bit is "0", the cpu owns the descriptor. the owner of the descriptor always owns the associated data frame. (the descriptor's frame start address field always points to this frame.) as it receives the data frame, software sets the maximum frame size register in the bdma block to the system frame buffer size (typically, to 1536 or 2048). software also sets the rx frame descriptor start address register to point to a chain of frame descriptors, all of which have their ownership bit set. the bdma engine can then be started to set the bdma receive enable bit in the bdmarxcon register. when a frame is received, it is copied into memory at the address specified by the rx frame start address. please note that no configurable offset or page boundary calculation is required. the received frame is written into the frame data buffer until the end of frame is reached, or until the length exceeds the configured maximum frame size. if the entire frame is received successfully, the status bits in the frame descriptor are set to indicate this. otherwise, the status bits are set to indicate that an error occurred. the ownership bit in the frame start address field is cleared and an interrupt may now be generated. the bdma controller copies the next frame descriptor register value into the rx frame descriptor start address register. if the next frame descriptor address is null (0), the bdma simply halts, and all subsequent frames are dropped. otherwise, the descriptor is read in, and the bdma controller starts again with the next frame, as described in the previous paragraph. if the received frame size exceeds the maximum frame size, the data frame will be overwritten by the last word of maximum frame. the overflow data is written to the rx status bit [19] in the receive frame descriptor. when the bdma reads a descriptor, if the ownership bit is not set, it has two options: ? skip to the next frame descriptor, or ? generate an interrupt and halt the bdma operation. transmit frame descriptors contain the following components: ? a four-byte pointer to the frame data ? widget alignment control bits [6:5] ? frame data pointer increment/decrement bit [4] ? little-endian control bit [3] ? interrupt enable after transmit [2] ? no-crc [1], and ? no-padding [0] during transmission, the two-byte frame length at the tx frame descriptor is moved into the bdma internal tx register. after transmission, tx status is saved in the tx frame descriptor. the bdma controller then updates the next frame descriptor address register for the linked list structure. when the tx frame descriptor start address register points to the first frame buffer, transmitter starts transmitting the frame data into the frame buffer memory.
S3C4530A ethernet c ontroller 7- 17 o frame data pointer reserved rx status frame length next frame descriptor pointer [31] ownership bit (o) 0 = cpu 1 = bdma [30:0] frame data pointer address of the frame data to be saved. [15:0] frame length the size of the received frame. [31:16] rx status the rx status field of the receive frame is updated by the mac after reception is complete. [31:0] next frame descriptor pointer address of next frame descriptor. 31 15 16 0 30 figure 7-6. data structure of rx frame descriptor
ethernet controller S3C4530A 7- 18 15 o 31 frame data pointer 16 reserved tx status frame length next frame descriptor pointer 0 [0] no-padding mode (p) 0 = padding mode 1 = no-padding mode [1] no-crc mode (c) 0 = crc mode 1 = no-crc mode [2] mac transmit interrupt enable after transmission of this frame (t) 0 = disable 1 = enable [3] little-endian mode (l) 0 = big-endian 1 = little-endian [4] frame data pointer increment/decrement (a) 0 = decrement 1 = increment [6:5] widget alignment control (wa) (non-aligned data must be transmitted without alignment control.) 00 = no invalid bytes 01 = one invalid byte 10 = two invalid bytes 11 = three invalid bytes [31] ownership bit (0) 0 = cpu 1 = bdma [30:0] frame data pointer the address of the frame data to be transmitted. [15:0] frame length the size of the transmit frame. [31:16] tx status this tx frame status field is updated by the mac after transmission. [31:0] next frame descriptor pointer the address of the next frame descriptor. 30 p c t l a wa 7 6 5 4 3 2 1 figure 7-7. data structure of tx frame descriptor
S3C4530A ethernet c ontroller 7- 19 [19] over maximum size (ovmax) set if the received frame data size exceeds the maximum frame size. [21] control received (ctlrcv) set if the received packet is a mac control frame. [22] interrupt on receive (intrx) set if reception of packet caused an interrupt condition. this includes good received, if the engood bit, macrxcon [14], is set. [23] receive 10 mb/s status (rx10stat) set if packet was received over the 7-wire interface. reset if packet was received over the mii. [24] alignment error (alignerr) frame length in bits was not a multiple of eight and the crc was invalid. [25] crc error (crcerr) crc at end of packet did not match the computed value, or else the phy asserted rx_er during packet reception. [26] overflow error (overflow) the mac receive fifo was full when it needed to store a received byte. [27] long error (longerr) received a frame longer than 1518 bytes. not set if the long enable bit set to one in the receive control register. [29] receive parity error (rxpar) mac receive fifo has detected a parity error. [30] good received (good) successfully received a packet with no errors. if engood = 1, an interrupt is generated on each packet that is received successfully. [31] reception halted (rxhalted) reception interrupted by user clearing rxen or setting haltlmm in the mac control register. 17 r x h a l t e d 31 16 30 g o o d r x p a r 0 l o n g e r r o v e r f l o w c r c e r r a l i g n e r r r x 1 0 s t a t i n t r x 0 o v m a x 0 0 0 29 28 27 26 25 24 23 22 21 c t i r c v 20 18 19 rx status figure 7-8. rx descriptor status bits
ethernet controller S3C4530A 7- 20 r x h a l t e d 31 16 [19:16] transmit collision count (txcollcnt) count of collisions during transmission of a single packet. after 16 collisions, txcoll is zero, and excoll is set. [20] excessive collision (excoll) 16 collisions occured in the same packet. [21] transmit deferred (txdefer) [22] paused [23] interrupt on transmit (inttx) set if transmission of packet caused an interrupt condition. this includes the enable completion (encomp), mactxcon [14], if enabled. [24] underrun (under) mac transmit fifo becomes empty during transmission. [25] deferral (defer) mac defers for max_deferral 0.32768ms for 100mbit/s or 3.27680ms for 10mbit/s. [26] no carrier (ncarr) carrier sense is not detected during the entire transmission of a packet (from the sfd to the crc). [27] sqe error (sqerr) after transmit frame, set if the fake collision (col) signal did not come from the phy for 1.6 m s. [28] late collision (latecoll) a collision occurred after 512 bit times (64 byte times) [29] transmit parity error (txpar) mac transmit fifo detected a parity error. [30] completion (comp) mac complete a transmit or discard of one packet. [31] transmission halted (txhalted) transmission halted by clearing rxen or setting the haltlmm in the mac control register. or, an interrupt was generated by an error condition (not completion). 30 c o m p t x p a r l a t e c o l l s q e r r n c a r r d e f e r u n d e r i n t t x p a u s e d e x c o l l txcollcnt 29 28 27 26 25 24 23 22 21 t x d e f e r 20 19 tx status figure 7-9. tx descriptor status bits
S3C4530A ethernet c ontroller 7- 21 frame descriptor start address register frame data pointer #1 status frame length next frame descriptor frame data pointer #2 status frame length next frame descriptor frame data #1 unused frame data #2 unused frame data #n (for ring type linked list) in single linked lists, the last next frame descriptor is filled with a null address memory for frame buffer bdmarxlsz bdmarxlsz receive frame maximum size register (bdmarxlsz) frame data pointer #n status next frame descriptor frame length figure 7-10. data structure of the receive frame data buffer
ethernet controller S3C4530A 7- 22 ethernet controller special registers the special registers used by the S3C4530A ethernet controller are divided into two main groups: ? bdma control and status registers ? mac control and status registers bdma control and status registers all registers that contain a memory address must store the address in a word-aligned format. table 7-2. bdma control and status registers registers offset r/w description reset value bdmatxcon 0x9000 r/w buffered dma transmit control register 0x00000000 bdmarxcon 0x9004 r/w buffered dma receive control register 0x00000000 bdmatxptr 0x9008 r/w transmit frame descriptor start address 0xffffffff bdmarxptr 0x900c r/w receive frame descriptor start address 0xffffffff bdmarxlsz 0x9010 r/w receive frame maximum size undefined bdmastat 0x9014 r/w buffered dma status 0x00000000 cam 0x9100?0x917c w cam content (32 words) undefined bdmatxbuf (1) 0x9200?0x92fc r/w bdma transmit (tx) buffer (64 words) for test mode addressing only undefined bdmarxbuf (1) 0x9800?0x98fc 0x9900?0x99fc r/w bdma receive (rx) buffer (64 words) for test mode addressing only undefined notes: 1. for testing, you can read the bdma tx/rx buffer directly. the bdma receive buffer has a 64 word by 33 bit size. the highest bit, [32], indicates the data frame boundary, as shown in the following illustration: 32 31 0 0x9800 0x98fc 0x9900 0x99fc eof (end of frame); boundary of frame data. figure 7-11. end of frame bit 2. you can access the eof bit by reading the address range, 0x9800-0x98fc (read into lsb bit 0).
S3C4530A ethernet c ontroller 7- 23 buffered dma transmit control register the buffered dma transmit control register, bdmatxcon, is described in tables 7-3 and 7-4 below. table 7-3. bdmatxcon register registers offset r/w description reset value bdmatxcon 0x9000 r/w buffered dma transmit control register 0x00000000 table 7-4. bdma transmit control register description bit number bit name description [4:0] bdma tx burst size (btxbrst) (word size + 1) of data bursts requested in bdma mode. by setting btxbrst as following values, y ou can select 4times of burst size by bit value. that is, you can select 1, 4, 8, 12, 16, 20, 24, 28, 32 word burst size. 0x00 - 0x02 word size is 0, that is, burst size is 1 word. 0x03 - 0x06 word size is 3, 4 words. 0x07 - 0x0a is 7, 8 words. 0x0b - 0x0e is 11, 12 words. 0x0f - 0x12 is 15, 16 words. 0x13 - 0x16 is 19, 20 words. 0x17 - 0x1a is 23, 24 words. 0x1b - 0x1e is 27, 28 words. 0x1f is 31, 32 words. [5] bdma tx stop/skip frame by owner bit (btxstsko) this bit determines whether the bdma tx controller issues an interrupt, if enabled, or skips the current frame and goes to the next frame descriptor (assuming bdma is not the owner). [6] reserved not applicable. [7] bdma tx complete to send control packet interrupt enable (btxccpie) setting this bit enables the bdma tx complete to send contol packet interrupt when the mac has finished sending the control packet. [8] bdma tx null list interrupt enable (btxnlie) this bit enables the bdma tx null list interrupt which indicates that the transmit frame descriptor start address pointer, bdmatxptr, in the bdma tx block has a null (0x00000000) address. [9] bdma tx not owner interrupt enable (btxnoie) this bit enables the bdma tx not owner interrupt when the ownership bit of the current frame does not belong to the bdma controller, and if the btxstsko bit is set. [10] bdma tx buffer empty interrupt enable (btxempty) set this bit is "1" to enable the tx buffer empty interrupt. [13:11] bdma transmit to mac tx start level (btxmsl) these bits determine when the new frame data in bdma tx buffer can be moved to the mac tx fifo when a new frame arrives. 000 means no wait, 001 means wait to fill 1/8 of the bdma tx buffer, 010 means wait to fill 2/8 of the buffer, and so on through 100 which means wait to fill 4/8 of the bdma tx buffer. note: if the last data of the frame arrives in bdma tx buffer, the data transfer from the bdma tx buffer to the mac tx fifo starts immediately, regardless of the level of these bits.
ethernet controller S3C4530A 7- 24 table 7-4. bdma transmit control register description (continued) bit number bit name description [14] bdma tx enable (btxen) when the tx enable bit is set to "1", the bdma tx block is enabled. even if this bit is disabled, buffer data will be moved to the mac tx fifo until the bdma tx buffer underflows (as long as the fifo is not empty and the mac tx is enabled). this bit is automatically disabled in the following cases: 1) if the next frame pointer is null, or 2) if the owner bit is zero, and the btxstsko bit is set. note: the frame descriptor start address pointer must be assigned before the bdma tx enable bit is set. [15] bdma tx reset (btxrs) set this bit to "1" to reset the bdma tx block.
S3C4530A ethernet c ontroller 7- 25 [4:0] bdma tx burst size (btxbrst) (word size + 1) of data bursts reqested in bdma mode. you can select 4times of burst size by bit value. that is, you can select 1, 4, 8, 12, 16, 20, 24, 28, 32 word burst size. 0x00 - 0x02 : 1 word burst size 0x03 - 0x06 : 4 word burst size 0x07 - 0x0a : 8 word burst size 0x0b - 0x0e : 12 word burst size 0x0f - 0x12 : 16 word burst size 0x13 - 0x16 : 20 word burst size 0x17 - 0x1a : 24 word burst size 0x1b - 0x1e : 28 word burst size 0x1f : 32 word burst size [5] bdma tx stop/skip frame by owner bit 0 = skips the current frame and goes to the next frame descriptor (if bdma is not the owner of the frame) 1 = bdma transmitter generates an interrupt (if enabled). [6] reserved [7] bdma tx complete to send control packet interrupt enable (btxccpie) 0 = disable complete to send control packet interrupt. 1 = enable complete to send control packet interrupt. (the interrupt is generated when the mac completes sending the control packet). [8] bdma tx null list interrupt enable 0 = disable transmit null list interrupt. 1 = enable null list interrupt to indicate that bdmatxptr in the bdma tx unit has a null address (0x00000000). [9] bdma tx not owner interrupt enable (btxnoie) 0 = disable bdma tx not owner interrupt for the current frame. 1 = enable bdma tx not owner interrupt for the current frame (and if the btxstsko bit is set). [10] bdma tx buffer empty interrupt (btxempty) 0 = disable tx buffer empty interrupt. 1 = enable tx buffer empty interrupt. [13:11] bdma transmit to mac tx start level (btxmsl) 000 = no waiting 001 = wait to fill 1/8 of the tx buffer 010 = wait to fill 2/8 of the tx buffer 011 = wait to fill 3/8 of the tx buffer 100 = wait to fill 4/8 of the tx buffer note: use this formula to calculate transmit time to the mac tx fifo tbtom: tbtom = (btxmsl/8) * size of the bdma tx buffer [14] bdma tx enable (btxen) 0 = disable the bdma transmitter. 1 = enable the bdma transmitter. [15] bdma tx reset (btxrs) 0 = no effect. 1 = reset the bdma tx block. reserved b t x r s b t x e n b t x m s l b t x e m p t y b t x n o i e b t x n l i e b t x c c p i e b t x s t s k o btxbrst 31 16 15 14 13 12 11 10 9 8 7 6 5 4 0 figure 7-12. buffered dma transmit control register
ethernet controller S3C4530A 7- 26 buffered dma receive control register the buffered dma receive control register, bdmarxcon, is described in tables 7-5 and 7-6 below. table 7-5. bdma rxcon register register offset address r/w description rest value bdmarxcon 0x9004 r/w buffered dma receive control register 0x00000000 table 7-6. bdma receive control register description bit number bit name description [4:0] bdma rx burst size (brxbrst) (word size + 1) of data bursts requested in bdma mode. by setting brxbrst as following values, y ou can select 4times of burst size by bit value. that is, you can select 1, 4, 8, 12, 16, 20, 24, 28, 32 word burst size. 0x00 - 0x02 word size is 0, that is, burst size is 1 word. 0x03 - 0x06 word size is 3, 4 words. 0x07 - 0x0a is 7, 8 words. 0x0b - 0x0e is 11, 12 words. 0x0f - 0x12 is 15, 16 words. 0x13 - 0x16 is 19, 20 words. 0x17 - 0x1a is 23, 24 words. 0x1b - 0x1e is 27, 28 words. 0x1f is 31, 32 words. [5] bdma rx stop/skip frame by owner bit (brxstsko) this bit determines whether the bdma rx controller issues an interrupt, if enabled, or skips the current frame and goes to the next frame descriptor (assuming bdma is not the owner). [6] bdma rx memory address inc/dec (brxmainc) this bit determines whether the address is incremented or decremented. if this bit is set to "1", the address will be incremented. [7] bdma rx every received frame interrupt enable (brxdie) this bit enables the bdma rx every received frame interrupt which is generated by the bdma controller each time is moves a complete data frame into memory. [8] bdma rx null list interrupt enable (brxnlie) this bit enables the bdma rx null list interrupt which indicates that the receive frame descriptor start address pointer, bdmarxptr, in the bdma rx block has a null (0x00000000) address. [9] bdma rx not owner interrupt enable (brxnoie) this bit enables the bdma rx not owner interrupt when the ownership bit of the current frame does not belong to the bdma controller, and if the brxstsko bit is set. [10] bdma rx maximum size over interrupt enable (brxmsoie) this bit enables the bdma rx maximum size over interrupt when the received frame size is larger than the value in receive frame maximum size register. [11] bdma rx big/little endian (brxlittle) this bit determines whether the data is stored in little- or big- endian format. if it is set to "1", word swapping will take place between the receive buffer and the system data bus. [13:12] bdma rx word alignment (brxwa) the rx word alignment bits determine how many bytes are invalid in the first word of each data frame. these invalid bytes are inserted when the word is assembled by the bdma controller. "00" = no invalid bytes, "01" = 1 invalid byte, "10" = 2 invalid bytes, and "11" = 3 invalid bytes.
S3C4530A ethernet c ontroller 7- 27
ethernet controller S3C4530A 7- 28 table 7-6. bdma receive control register description (continued) bit number bit name description [14] bdma rx enable (brxen) when the rx enable bit is set to "1", the bdma rx block is enabled. even if this bit is disabled, the mac will receive rx data until the mac rx fifo overflows (as long as the fifo is not empty and the mac rx is enabled). this bit is automatically disabled in the following cases: 1) if the next frame pointer is null, or 2) if the owner bit is zero, and the brxstsko bit is set. note: the frame descriptor start address pointer must be assigned before the bdma rx enable bit is set. [15] bdma rx reset (brxrs) set this bit to "1" to reset the bdma rx block. [16] bdma rx buffer empty interrupt enable (brxempty) set this bit is "1" to enable the rx buffer empty interrupt. [17] bdma rx early notify interrupt enable (brxearly) set this bit to "1" to enable the rx early notify interrupt. the function of this interrupt is to note the length of a data frame that is being received from its frame length field.
S3C4530A ethernet c ontroller 7- 29 reserved b r x e a r l y b r x e m p t y b r x r s b r x e n b r x w a b r x l i t t l e b r x m s o i e b r x n o i e b r x n l i e b r x d i e b r x m a i n c b r x s t s k o b r x s t s k o brxbrst 31 18 17 16 15 14 13 12 [4:0] bdma rx burst size (brxbrst) (word size + 1) of data bursts reqested in bdma mode. you can select 4times of burst size by bit value. that is, you can select 1, 4, 8, 12, 16, 20, 24, 28, 32 word burst size. 0x00 - 0x02 : 1 word burst size 0x03 - 0x06 : 4 word burst size 0x07 - 0x0a : 8 word burst size 0x0b - 0x0e : 12 word burst size 0x0f - 0x12 : 16 word burst size 0x13 - 0x16 : 20 word burst size 0x17 - 0x1a : 24 word burst size 0x1b - 0x1e : 28 word burst size 0x1f : 32 word burst size [5] bdma rx stop/skip frame (or interrupt if not owner of the current frame (brxstsko) 0 = skips the current frame and goes to the next frame descriptor. 1 = bdma receiver generates an interrupt (if enabled). [6] bdma rx memory address increment/decrement (drxmainc) 0 = decrement the frame memory address. 1 = increment the frame memory address. [7] bdma rx every receuve frane interrupt enable (brxdie) 0 = disable frame receive done interrupt. 1 = enable frame receive done interrupt. [8] bdma rx null list interrupt enable (brxnlie) 0 = disable null address (0x00000000) receive interrupt. 1 = enable null address (0x00000000) receive interrupt. [9] bdma rx not owner interrupt enable (brxmsoie) 0 = disable interrupt for bdma rx not owner of the current frame. 1 = enable interrupt for bdma rx not onwer of the current frame. [10] bdma rx maximum size over interrupt enable (brxmsoie) 0 = disable interrupt for received frame if larger than the maximum frame size. 1 = enable interrupt for received frame if larger than the maximum frmae size. [11] bdma rx big/little endian (brxlittle) 0 = big-endian frame data format. 1 = little-endian. (frame data in bdma rx buffer is word-swapped on the system bus). [13:12] bdma rx word alignment (brxwa) 00 = do not insert an invalid byte in the first received frame data. 01 = insert one invalid byte in the first received frame data. 10 = insert two invalid bytes in the firat received frame data. 11 = insert three invalid bytes in the first received frame data. [14] bdma rx enable (brxen) 0 = disable the bdma receiver. (if the mac rx fifo is not empty, move data to the bdma rx buffer). 1 = enable the bdma receiver. [15] bdma rx reset (brxrs) 0 = no effect. 1 = reset the bdma receiver. [16] bdma rx buffer empty interrupt (rxempty) 0 = disable the rx buffer empty interrupt. 1 = enable the rx buffer empty interrupt. [17] bdma rx early notify interrupt (brxearly) 0 = disable the rx early notify interrupt. 1 = enable the interrupt when bdma captures the length of the received frame type. bdmarxcon register figure 7-13. buffered dma receiver control register
ethernet controller S3C4530A 7- 30 bdma transmit frame descriptor start address register table 7-7. bdmatxptr register registers offset r/w description reset value bdmatxptr 0x9008 r/w buffered dma transmit control register 0xffffffff table 7-8. bdma transmit frame descriptor start address register description bit number bit name description [25:0] bdma transmit frame descriptor start address the bdma transmit frame descriptor start address register contains the address of the frame descriptor on the frame to be sent. during a bdma operation, this start address pointer is updated to the next frame address. bdma receive frame descriptor start address register table 7-9. bdmarxptr register registers offset r/w description reset value bdmarxptr 0x900c r/w buffered dma transmit control register 0xffffffff table 7-10. bdma receive frame descriptor start address register description bit number bit name description [25:0] bdma receive frame descriptor start address the bdma receive frame descriptor start address register contains the address of the frame descriptor on the frame to be saved. during a bdma operation, this start address pointer is updated to the next frame address.
S3C4530A ethernet c ontroller 7- 31 bdma receive frame maximum size register table 7-11. bdmarxlsz register registers offset r/w description reset value bdmarxlsz 0x9010 r/w receive frame maximum size undefined table 7-12. bdma receive frame maximum size register description bit number bit name description [15:0] bdma receive frame maximum size (brxlsz) this register value controls how many bytes per frame can be saved to memory. if the received frame size exceeds the value stored in this location, an error condition is reported. [31:16] bdma receive frame length (brxfsz), read-only when an early notification (early notify) interrupt occurs, the frame length/ethernet type field contains the frame size of the frame that is currently being received. to save space in the frame memory buffer, you can determine the current frame length by 1) enabling the early notification interrupt, and 2) reading the brxfsz field when the interrupt occurs. to calculate the value of the next frame start address pointer, you add the current frame size value (brxfsz) to the bdma receive start address register. (for a control packet, additional space may be needed.) note: to obtain the next rx frame address that is to be saved in the rx frame start address register, we recommend that you first halt the bdma operation. bdma status register table 7-13. bdmastat register registers offset r/w description reset value bdmastat 0x9014 r/w buffered dma status 0x00000000
ethernet controller S3C4530A 7- 32 table 7-14. bdma status register description bit number bit name description [0] bdma rx done every received frame (brxrdf) this bit is set each time the bdma receiver moves one received data frame to memory. this bit must be cleared for the receiving next frame interrupt generation. [1] bdma rx null list (brxnl) if this bit is set, the bdmarxptr has a null address. even if bdma rx is disabled, data is transferred from the mac rx fifo to the bdma rx buffer until the bdma rx buffer overflows. [2] bdma rx not owner (brxno) if this bit is set, bdma is not the owner of the current data frame. the brxstsko bit is set and bdma rx is stopped. [3] bdma rx maximum size over (brxmso) if this bit is set, the received frame size is larger than the value in the rx frame maximum size register, bdmarxlsz. [4] bdma rx buffer empty (brxempty) if this bit is set, the bdma rx buffer is empty. [5] early notification (brxsearly) this bit is set when the bdma receiver has received the length/ether-type field of the current frame. [6] reserved not applicable. [7] one more frame data in bdma receive buffer (brxfrf) this bit is set whenever an additional data frame is received in the bdma receive buffer. [15:8] number of frames in bdma receive buffer (brxnfr) this value indicates the total number of data frames currently in the bdma receive buffer. [16] bdma tx complete to send control packet (btxccp) bit [16] is set each time the mac sends a complete control packet. [17] bdma tx null list (btxnl) if this bit is set, the bdmatxptr value is a null address. in this case, bdma tx is disabled but data continues to be transferred from the bdma tx buffer to the mac tx fifo until the bdma tx buffer underflows. this bit is read only. if you set bdma tx reset bit by software, this bit is cleared automatically. to resume data transfer, you must then set the new frame descriptor pointer and enable bdma tx. [18] bdma tx not owner (btxno) if [18] is set, bdma is not owner of the current frame. in this case, the bstsko bit is set and bdma tx is stopped. [19] reserved not applicable. [20] bdma tx buffer empty (btxempty) if this bit is set, the bdma tx buffer is empty. [31:21] reserved not applicable.
S3C4530A ethernet c ontroller 7- 33 31 16 15 [0] bdma rx done evert received frame (brxrdf) 0 = reset frame data receive state. 1 = receipt of the data frame is complete. [1] bdma rx null list (brxnl) 0 = reset state of new frame descriptor (bdmarxptr) is set. 1 = current frame descriptor address is null (0x00000000). [2] bdma rx not owner (brxno) 0 = bdma is owner of the current frame. 1 = the owner of the current frame is not bdma (cpu). in this case, bdma rx is stopped and the bstsko bit is set. [3] bdma rx maximum size over (brxmso) 0 = reset state or next frame arrived at bdma rx buffer. 1 = received frame exceeds the maximum frame size. [4] bdma rx buffer empty (brxempty) 0 = not empty. 1 = bdma rx buffer empty. [5] early notify (brxsearly) 0 = normal operation. 1 = lengthe of current frame can be accessed by reading the bdma receive maximum frame size register, bdmarxlsz [31:16]. [7] one more frame data in bdma receive buffer (brxfrf) 0 = only one frame data in bdma receive buffer. 1 = one more frame data was in the bdma receive buffer. [15:8] number of frame data in bdma receive buffer (brxnfr) [16] bdma tx complete to send control packet (btxccp) 0 = clear but by writing a 1 to this bit or by resetting bdma tx. 1 = mac complete to send the control packet. [17] bdma tx null list (btxnl) 0 = reset stste of new frame descriptor (bdmatxptr) is set. 1 = current frame descriptor address is null (0x00000000). [18] bdma tx not owner (btxno) 0 = bdma is owner of the current frame. 1 = the owner of the current frame is not bdma (cpu). in this case, bdma tx is stopped if the btxstsko bit is set to one. [19] reserved [20] bdma tx buffer empty (btxempty) 0 = not empty 1 = bdma tx buffer empty. [31:21] reserved note: bit 0, 1, 2, 3, 4, 16, 17, 18 and 20 should be cleared for interrupt generation for the next frame. the method is write 1 to the corresponding bit location. 8 7 6 5 4 0 21 20 19 18 17 3 2 1 reserved brxnfr b r x f r f x b r x s e a r l y b t x e m p t y x b t x n o b t x n l b t x c c p b r x e m p t y b r x m s o b r x n o b r x n l b r x r d f figure 7-14. bdma status register
ethernet controller S3C4530A 7- 34 content address memory (cam) register there are 21 cam entries for the destination address and the pause control packet. for the destination address cam value, one destination address consists of 6 bytes. using the 32-word space (32 4 bytes), you can therefore maintain up to 21 separate destination addresses. you use cam entries 0, 1, and 18 to send pause control packets. to send a pause control packet, you write the cam0 entry with the destination address, the cam1 entry with the source address, and the cam 18 entry with length/type, opcode, and operand. you then set the send pause bit in the mac transmit control register. table 7-15. cam register registers offset r/w description reset value cam 0x9100?0x917c w cam content (32 words) undefined table 7-16. content address memory (cam) register description bit number bit name description [31:0] cam content (cam) the cpu uses the cam content register as a data base for destination address. to activate the cam function, you must set the appropriate enable bits in cam enable register.
S3C4530A ethernet c ontroller 7- 35 media access control (mac) registers this section describes the control and status registers for the flow control 100-/10-mbit/s ethernet mac. these include a master mac control register, control registers for transmit and receive, control registers for the cam, a counter for network management, and various flow control registers (see table 7-17). table 7-17. mac control and status registers registers offset r/w description reset value macon 0xa000 r/w mac control 0x00000000 camcon 0xa004 r/w cam control 0x00000000 mactxcon 0xa008 r/w transmit control 0x00000000 mactxstat 0xa00c r/w transmit status 0x00000000 macrxcon 0xa010 r/w receive control 0x00000000 macrxstat 0xa014 r/w receive status 0x00000000 stadata 0xa018 r/w station management data 0x00000000 stacon 0xa01c r/w station management control and address 0x00006000 camen 0xa028 r/w cam enable 0x00000000 emisscnt 0xa03c rclr/w missed error count 0x00000000 epzcnt 0xa040 r pause count 0x00000000 ermpzcnt 0xa044 r remote pause count 0x00000000 etxstat 0x9040 r transmit control frame status 0x00000000 note: mac transmit/receive i nterrupt is generated whenever the tx/rx status field of tx/rx frame descriptor is written.
ethernet controller S3C4530A 7- 36 mac control register the mac control register provides global control and status information for the mac. the missed roll/link10 bit is a status bit. all other bits are mac control bits. mac control register settings affect both transmission and reception. you can also control transmit and receive operations separately. to select customized operating features, you should write this register during power-up. this way, you will not need to write or read it again during normal operation. after a reset is complete, the mac controller clears the reset bit. not all phys support full-duplex operation. (setting the mac loopback bit overrides the full-duplex bit.) also, some 10-mb/s phys may interpret the loop10 bit to control different functions, and manipulate the link10 bit to indicate a different status condition. table 7-18. macon register registers offset r/w description reset value macon 0xa000 r/w mac control 0x00000000 table 7-19. mac control register description bit number bit name description [0] halt request (haltreq) set this bit to stop data packet transmission and reception as soon as tx/rx of any current packets has been completed. [1] halt immediate (haltimm) set this bit to immediately stop all transmission and reception. [2] software reset (reset) set this bit to reset all mac control and status register and mac state machines. [3] full-duplex (fulldup) set this bit to start transmission while reception is in progress. [4] mac loopback (macloop) set this bit to cause transmission signals to be presented as input to the receive circuit without leaving the controller. [5] reserved not applicable [6] mii-off use this bit to select the connection mode. if this bit is set to one, 10 m bits/s interface will select the 10 m bits/s endec. otherwise, the mii will be selected. [7] loop 10 mb/s (loop10) if this bit is set, the loop_10 external signal is asserted to the 10-mb/s endec. [9:8] reserved not applicable. [10] missed roll (missroll) this bit is automatically set when the missed error counter rolls over. [11] reserved not applicable. [12] mdc-off clear this bit to enable the mdc clock generation for power management. if it is set to one, the mdc clock generation is disabled. [13] enable missed roll (enmissroll) set this bit to generate an interrupt whenever the missed error counter rolls over. [14] reserved not applicable [15] link status 10 mb/s (link10) this bit value is read as a buffered signal on the link 10 pin. [31:16] reserved not applicable.
S3C4530A ethernet c ontroller 7- 37 cam control register the three accept bits in the cam control register are used to override cam rejections. to place the mac in promiscuous mode, use cam control register settings to accept packets with all three types of destination addresses. the three types of destination address packets are as follows: ? station packets, which has an even first byte. for example, 00-00-00-00-00-00. ? a multicast-group, which has an odd first byte, but which is not ff-ff-ff-ff-ff-ff. for example, 01-00-00- 00-00-00. ? a broadcast, defined as ff-ff-ff-ff-ff-ff. when you enable cam compare mode, the cam memory reads the destination addresses to filter incoming messages. (you will recall that the cam memory consists of 6-byte entries.) an alternative way to place the mac in promiscuous mode is to set, in turn, to accept the them. to reject all packets, simply clear all of the bits in the camcon register. table 7-20. camcon register registers offset r/w description reset value camcon 0xa004 r/w cam control 0x00000000 table 7-21. cam control register description bit number bit name description [0] station accept (stationacc) set this bit to accept any packet with a " unicast" station address. [1] group accept (groupacc) accept any packet with a multicast-group address. [2] broadcast accept (broadacc) accept any packet with a broadcast address. [3] negative cam (negcam) when this bit is "0", packets the cam recognizes are accepted and others are rejected. when "1", packets the cam recognizes are rejected and others are accepted. [4] compare enable (compen) set this bit to enable compare mode. [31:5] reserved not applicable.
ethernet controller S3C4530A 7- 38 mac transmit control register to generate an interrupt after each packet, set the enable completion bit and all of the mac error enable bits. using mac transmit control register settings, you can also selectively enable interrupts for specific conditions. table 7-22. mactxcon register registers offset r/w description reset value mactxcon 0xa008 r/w transmit control 0x00000000 table 7-23. mac transmit control register description bit number bit name description [0] transmit enable (txen) set this bit to enable transmission. to stop transmission immediately, clear the transmit enable bit to "0". [1] transmit halt request (txhalt) set this bit to halt transmission after completing any current packet. [2] suppress padding (nopad) set to not generate pad bytes for packets of less than 64 bytes. [3] suppress crc (nocrc) set to suppress addition of a crc at the end of a packet. [4] fast back-off (fback) set this bit to use faster back-off times for testing. [5] no defer (nodef) set to disable the defer counter. (the defer counter keeps counting until the carrier sense (crs) bit is turned off.) [6] send pause (sdpause) set this bit to send a pause command or other mac control packet. the send pause bit is automatically cleared when a complete mac control packet has been transmitted. writing a "0" to this register bit has no effect. [7] mii 10-mb/s sqe test mode enable (sqen) set this bit to enable mii 10-mb/s sqe test mode. [8] enable underrun (enunder) set this bit to generate an interrupt if the mac transmit fifo is empty during a transmission. [9] enable deferral (endefer) set this bit to generate an interrupt if the mac defers for max_deferral time: "0" = 0.32768 ms at 100 mb/s; "1" = 3.2768 ms at 10-mb/s. [10] enable no carrier (enncarr) set this bit to generate an interrupt if a carrier sense is not detected while an entire packet is transmitted. [11] enable excessive collision (enexcoll) set this bit to enable an interrupt if 16 collisions occur in the same packet. [12] enable late collision (enlatecoll) set this bit to generate an interrupt if a collision occurs after 512 bit times (or 64 byte times). [13] enable transmit parity (entxpar) set this bit to generate an interrupt if a parity error is detected in the mac transmit fifo. [14] enable completion (encomp) set this bit to generate an interrupt whenever the mac transmits or discards one packet. [31:15] reserved not applicable.
S3C4530A ethernet c ontroller 7- 39 mac transmit status register a transmission status flag is set in the transmit status register, mactxstat, whenever the corresponding event occurs. in addition, an interrupt is generated if the corresponding enable bit in the transmit control register is set. a mac transmit fifo parity error sets txpar, and also clears txen, if the interrupt is enabled. you can read and mask the five low-order bits as a single collision count. that is, when excoll is "1", txcoll is "0". if txcoll is not "0", then excoll is "0". table 7-24. mactxstat register registers offset r/w description reset value mactxstat 0xa00c r/w transmit status 0x00000000 table 7-25. mac transmit status register description bit number bit name description [3:0] transmit collision count (txcoll) this 4-bit value is the count of collisions that occurred while successfully transmitting the packet. [4] excessive collision (excoll) this bit is set if 16 collisions occur while transmitting the same packet. in this case, packet transmission is aborted. [5] transmit deferred (txdeferred) this bit is set if transmission of a packet was deferred because of a delay during transmission. [6] paused (paused) this bit is set if transmission of a packet was delayed due to a pause being received. [7] interrupt on transmit (inttx) this bit is set if transmission of a packet causes an interrupt condition. [8] underrun (under) this bit is set if the mac transmit fifo becomes empty during a packet transmission. [9] deferral (defer) this bit is set if the mac defers a transfer because of max_deferral at 0.32768 ms for 100 mb/s or 3.2768 ms for 10mb/s. [10] no carrier (ncarr) this bit is set if no carrier sense is detected during the transmission a packet. [11] signal quality error (sqe) according to the ieee802.3 rule, the sqe signal reports the status of the pma (mau or transceiver) operation to the mac layer. after transmission is complete and 1.6 m s has elapsed, a collision detection signal is issued for 1.5 m s to the mac layer. this signal is called the sqe test signal. the mac sets the sqe bit in the mactxstat register if this signal is not reported within the ifg time of 6.4 m s. [12] late collision (latecoll) this bit is set if a collision occurs after 512 bit times (or 64 byte times). [13] transmit parity error (txpar) this bit is set if a collision occurs after 512 bit times (or 64 byte times). [14] completion (comp) this bit is set when the mac transmits, or discards, one packet. [15] transmission halted (txhalted) transmission was halted by clearing the txen bit or the halt immediate (haltimm) bit. [31:16] reserved not applicable.
ethernet controller S3C4530A 7- 40 mac receive control register to issue an interrupt after each packet is received, set the enable good bit and all of the error enable bits in the macrxcon register. you can also enable interrupts for specific conditions. standard packet length values do not include a preamble or a start frame delimiter (sfd). table 7-26. macrxcon register registers offset r/w description reset value macrxcon 0xa010 r/w receive control 0x00000000 table 7-27. mac receive control register description bit number bit name description [0] receive enable (rxen) set this bit to "1" to enable mac receive operation. if "0", stop reception immediately. [1] receive halt request (rxhalt) set this bit to halt reception after completing the reception of any current packet. [2] long enable (longen) set this bit to receive frames with lengths greater than 1518 bytes. [3] short enable (shorten) set this bit to receive frames with lengths less than 64 bytes. [4] strip crc value (stripcrc) set this bit to check the crc, and then strip it from the message. [5] pass control packet (passctl) set this bit to enable the passing of control packets to a mac client. [6] ignore crc value (ignorecrc) set this bit to disable crc value checking. [7] reserved not applicable. [8] enable alignment (enalign) set this bit to enable the alignment interrupt. an alignment interrupt occurs when a packet is received whose length (in bits) is not a multiple of eight, and whose crc is invalid. [9] enable crc error (encrcerr) set this bit to enable the crc interrupt. a crc interrupt occurs when a packet is received whose crc is invalid or if, during its reception, the phy asserts rx_er. [10] enable overflow (enover) set this bit to enable the overflow interrupt. an overflow interrupt is generated when a packet is received and the mac receive fifo is full. [11] enable long error (enlongerr) set this bit to enable the long error interrupt. a long error interrupt is generated when a frame longer than 1518 bytes is received (unless the long enable bit is set). [12] reserved not applicable. [13] enable receive parity (enrxpar) set this bit to enable a receive parity interrupt if the mac receive fifo detects a parity error. [14] enable good (engood) set this bit to enable the good (packet) interrupt upon error-free reception of a complete data packet. [31:15] reserved not applicable. note: the frame lengths given above do not include preamble and start frame delimiter (sfd).
S3C4530A ethernet c ontroller 7- 41 mac receive status register a receive status flag is set in the mac receive status register, macrxstat, whenever the corresponding event occurs. when a status flag is set, it remains set until another packet arrives, or until software writes a "1" to the flag to clear the status bit. if the corresponding interrupt enable bit in the receive control register is set, an interrupt is generated whenever a status flag is set. a mac receive parity error sets rxpar, and also clears the rxen bit (if an interrupt is enabled). table 7-28. macrxstat register registers offset r/w description reset value macrxstat 0xa014 r/w receive status 0x00000000 table 7-29. mac receive status register description bit number bit name description [4:0] reserved not applicable. [5] control frame received (ctlrecd) this bit is set if the packet received is a mac control frame (type = 8808h), if the cam recognizes the packet address, and if the frame length is 64 bytes. [6] interrupt on receive (intrx) this bit is set if the reception of a packet caused an interrupt to be generated. this includes a good received interrupt, if the engood bit is set. [7] receive 10-mb/s status (rx10stat) this bit is set to "1" if a packet was received over the 7-wire interface or to "0" if a packet was received over the mii. [8] alignment error (alignerr) this bit is set if the frame length in bits was not a multiple of eight and the crc was invalid. [9] crc error (crcerr) this bit is set if the crc at the end of a packet did not match the computed value, or else the phy asserted rx_er during packet reception. [10] overflow error (overflow) this bit is set if the mac receive fifo was full when it needed to store a received byte. [11] long error (longerr) this bit is set if the mac received a frame longer than 1518 bytes. (it is not set if the long enable bit in the receive control register, macrxcon, is set.) [12] reserved not applicable. [13] receive parity error (rxpar) this bit is set if a parity error is detected in the mac receive fifo. [14] good received (good) this bit is set if a packet was successfully received with no errors. if engood = "1", an interrupt is also generated. [15] reception halted (rxhalted) this bit is set if reception was halted by clearing rxen or by setting the haltimm bit in the mac control register, macon. [31:16] reserved not applicable.
ethernet controller S3C4530A 7- 42 mac station management data register table 7-30. stadata register registers offset r/w description reset value stadata 0xa018 r/w station management data 0x00000000 table 7-31. station management register description bit number bit name description [15:0] station management data. this register contains a 16-bit data value for the station management function.
S3C4530A ethernet c ontroller 7- 43 mac station management data control and address register the mac controller provides support for reading and writing station management data to the phy. setting options in station management registers does not affect the controller. some phys may not support the option to suppress preambles after the first operation. table 7-32. stacon register registers offset r/w description reset value stacon 0xa01c r/w station management control and address 0x00008000 table 7-33. stacon register description bit number bit name description [4:0] phy register address (addr) a 5-bit address, contained in the phy, of the register to be read or written. [9:5] phy address (phy) the 5-bit address of the phy device to be read or written. [10] write (wr) to initiate a write operation, set this bit to "1". for a read operation, clear it to "0". [11] busy bit (busy) to start a read or write operation, set this bit to "1". the mac controller clears the busy bit automatically when the operation is completed. [12] preamble suppress (presup) if you set this bit, the preamble is not sent to the phy. if it is clear, the preamble is sent. [15:13] mdc clock rating control the mdc period. md_ca[15:13] mdc period 000 16 (1/fmclk) 001 18 (1/fmclk) 010 20 (1/fmclk) . . . . 111 30 (1/fmclk) mdc period = md_ca[15:13] 2 + 16 default mdc_ca[15:13] = 100 [31:16] reserved not applicable.
ethernet controller S3C4530A 7- 44 cam enable register the cam enable register, camen, indicates which cam entries are valid, using a direct comparison mode. up to 21 entries, numbered 0 through 20, may be active, depending on the cam size. if the cam is smaller than 21 entries, the higher bits are ignored. table 7-34. camen register registers offset r/w description reset value camen 0xa028 r/w cam enable 0x00000000 table 7-35. cam enable register description bit number bit name description [20:0] cam enable (camen) set the bits in this 21-bit value to selectively enable cam locations 20 through 0. to disable a cam location, clear the appropriate bit. [31:21] reserved not applicable.
S3C4530A ethernet c ontroller 7- 45 mac missed error count register the value in the missed error count register, emisscnt, indicates the number of packets that were discarded due to various type of errors. together with status information on packets transmitted and received, the missed error count register and the two pause count registers provide the information required for station management. reading the missed error counter register clears the register. it is then the responsibility of software to maintain a global count with more bits of precision. the counter rolls over from 0x7fff to 0x8000 and sets the corresponding bit in the mac control register. it also generates an interrupt if the corresponding interrupt enable bit is set. if station management software wants more frequent interrupts, you can set the missed error count register to a value closer to the rollover value of 0x7fff. for example, setting a register to 0x7f00 would generate an interrupt when the count value reaches 256 occurrences. table 7-36. emisscnt register registers offset r/w description reset value emisscnt 0xa03c r(clr)/w missed error count 0x00000000 table 7-37. missed error count register description bit number bit name description [15:0] alignment error count (alignerrcnt) the number of packets received with alignment errors. this software counter increments at the end of a packet reception if the rx_stat value indicates an alignment error. crc error count (crcerrcnt) the number of packets received with a crc error. this software counter increments if the rx_stat value indicates a crc error. if the rx_stat value indicates another type of error, such as an alignment error, this counter is not incremented. missed error count (misserrcnt) the number of valid packets rejected by the mac unit because of mac receive fifo overflows, parity errors, or because the rx_en bit was cleared. this count does not include the number of packets rejected by the cam. [31:16] reserved not applicable.
ethernet controller S3C4530A 7- 46 mac received pause count register the received pause count register, epzcnt, stores the current value of the 16-bit received pause counter. table 7-38. epzcnt register registers offset r/w description reset value epzcnt 0xa040 r pause count 0x00000000 table 7-39. received pause count register description bit number bit name description [15:0] received pause count (epzcnt) the count value indicates the number of time slots the transmitter was paused due to the receipt of control pause operation packets from the mac. mac remote pause count register the remote pause count register, ermpzcnt, stores the current value of the 16-bit remote puase counter. table 7-40. ermpzcnt register registers offset r/w description reset value ermpzcnt 0xa044 r remote pause count 0x00000000 table 7-41. remote pause count register description bit number bit name description [15:0] received pause count (epzcnt) the count value indicates the number of time slots that a remote mac was paused as a result of its sending control pause operation packets.
S3C4530A ethernet c ontroller 7- 47 mac transmit control frame status the transmit control frame status register, etxstat, is a ram-based register which provides the status of a mac control packet as it is sent to a remote station. this operation is controlled by the sdpause bit in the transmit control register, mactxcon. it is the responsibility of the dma engine to read this register, and to generate an interrupt to notify the system that the transmission of a mac control packet has been completed. table 7-42. etxstat register registers offset r/w description reset value etxstat 0x9040 r transmit control frame status 0x00000000 table 7-43. transmit control frame register description bit number bit name description [15:0] tx_stat value a 16-bit value indicating the status of a mac control packet as it is sent to a remote station. read by the dma engine.
ethernet controller S3C4530A 7- 48 ethernet controller operations this section contains additional details about the following operations of the S3C4530A ethernet controller: ? mac frame and packet formats ? transmitting a frame ? receiving a frame ? full-duplex pause operation ? error signalling and network management mac frame and packet formats the mac transmits each byte of all fields, except the fcs, least-significant bit first. in this document, the term "packet" is used to denote all of the bytes that are transmitted and received, while "frame" refers only to the bytes delivered by the station for transmission, and to the station who is receiving. table 7-44 lists the eight fields in a standard data packet (ieee 802.3/ethernet frame). see also figure 7-13. table 7-44. mac frame and package format description field name field size description preamble 7 bytes the bits in each preamble byte are 10101010, transmitted from left to right. start frame delimiter (sfd) 1 byte the sfd bits are 10101011, transmitted from left to right. destination address 6 bytes the destination address can be an individual address or a multicast (or broadcast) address. source address 6 bytes the mac does not interpret the source address bytes. however, to qualify as a valid station address, the first bit transmitted (the lsb of the first byte) must be a "0". length or type 2 bytes the mac treats length fields greater than 1500 bytes as type fields. byte values less than or equal to 1500 indicate the number of logical link control (llc) data bytes in the data field. the mac transmits the high-order byte first. logical link control (llc) data 46 to 1500 bytes data bytes used for logical link control. pad 0 to 46 bytes if the llc data is less than 46 bytes long, the mac transmits pad bytes of all zeros. frame check sequence (fcs) 4 bytes the fcs field contains a 16-bit error detection code that is computed as a function of all fields except the preamble, the sfd, and the fcs itself. the fcs - 32 polynomial function is as follows: " x32 + x26 + x23 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x1 + 1".
S3C4530A ethernet c ontroller 7- 49 packet (encoded on the medium) added by transmitter, stripped by receiver data frame (sent by user) added by transmitter data frame (delivered to user) optionaly stripped by receiver preamble s f d destination address source address length or type llc data pad fcs 4 bytes 0-46 46-1500 bytes 2 bytes 6 bytes 6 bytes 1 7 bit llc header llc information field dsap ssap ctrl ip/x.25/...... snap dsap ssap ctrl oui pid ip/x.25/...... 1 byte 1 byte 1 byte 3 bytes 2 bytes dsap = destination service access point ctrl = control field oui = origanizationally unique identifier sfd = starting frame delimiter ssap = source service access point snap = subnetwork access protocol pid = protocol identifier llc = logical lick control fcs = frame check sequence or figure 7-15. fields of an ieee802.3/ethernet packet (frame) options that affect the standard mac frame there are a number of factors and options which can affect the standard mac frame, as described in table 7-44: ? some phys may deliver a longer or shorter preamble. ? short packet mode permits llc data fields with less than 46 bytes. options are available to suppress padding and to support the reception of short packets. ? long packet mode supports llc data fields with more than 1500 bytes. an option is also available to support to reception of long packets. ? "no crc" mode s uppresses the appending of a crc field. ? "ignore crc" mode allows the reception of packets without valid crc fields.
ethernet controller S3C4530A 7- 50 destination address format bit 0 of the destination address is an address type designation bit. it identifies the address as either an individual or a group address. group addresses are sometimes called "multicast" addresses and individual addresses are called "unicast" addresses. the broadcast address is a special group address in the special hex format: ff-ff- ff-ff-ff-ff. bit 1 of the destination address distinguishes between locally or globally administered addresses. for globally administered or universal (u) addresses, the bit value is "0". if an address is to be assigned locally, you must set this bit to "1". for the broadcast address, this bit must also be set to "1". destination address block id or oui (3 bytes) mac address (3 bytes) u/l i/g [0] individual or group flag (i/g) 0 = individual (= unicast) address. 1 = group (= multicast) address. [1] universal or local address flag (u/l) 0 = universal address. 1 = local address. figure 7-16. destination address format special flow control destination address the current specification for full-duplex flow control specifies a special destination address for the pause operation packet. in order for the mac to receive packets which contain this special destination address, the address must be programmed in one of the cam entries. this cam entry must then be enabled, and the cam activated. some cam entries are also used when generating a flow control packet using the sdpause bit in the mac transmit control register.
S3C4530A ethernet c ontroller 7- 51 transmitting a frame to transmit a frame, the transmit enable bit in the transmit control register must be set and the transmit halt request bit must be zero. in addition, the halt immediate and halt request bits in the mac control register must be "0". these conditions are normally set after any bdma controller initialization has occurred. the system then uses the tx_wr# and tx_eof signals to transfer bytes to the transmit data buffer. the transmit state machine starts transmitting the data in the fifo, and will retain the first 64 bytes until after this station has acquired the net. at that time, the transmit block requests more data and transmits it until the system asserts the tx_eof input, signaling the end of data to be transmitted. the transmit block appends the calculated crc to the end of the packet, and transmission ends. it then sets the transmit status register bit 0, signaling a successful transmission. this action may causes an interrupt, if enabled. a frame transmit operation can be subdivided into two operations, 1) a mii interface operation, and 2) a bdma/ mac interface operation. bdi transmit operation the bdi transmit operation is a simple fifo mechanism. the bdma engine stores data to be transmitted, and the transmit state machine empties it when the mac successfully acquires the net. note that the two time domains intersect at the fifo controller. the writing and reading of data is asynchronous and on different clocks. reading is driven by either a 25-mhz or a 2.5-mhz transmit clock. writing is driven by the synchronous sys_clk, which is asynchronous to tx_clk. after a reset, the transmit fifo is empty. the transmit block asserts the tx_rdy signal, and transmission is disabled. to enable transmission, the system must set the transmit enable bit in the transmit control register. in addition, eight bytes of data must be present in the transmit fifo. the bdma engine can start stuffing data into the fifo, and then enable the transmit bit. (or it can enable the transmit bit first and then start stuffing data into the fifo.) the transmit operation can only start if both of these conditions are met.
ethernet controller S3C4530A 7- 52 bdi transmit timing when the transmit block asserts the tx_rdy signal, the bdma engine can write data into the transmit fifo by asserting the tx_wr# signal. figure 7-15 shows timing sequences for back-to-back transfers and transfers with wait states. this is a synchronous interface, which means that data is latched in at the rising edge of the sys_clk when tx_wr# is asserted. for slower interfaces, the rising edge of tx_wr# can be delayed. this is the equivalent of asserting a wait state in a synchronous operation. the transmit fifo machine checks the tx_par and the tx_eof bits. if there is a parity error, the transmit block aborts the transmission, resets the fifo, and generates an interrupt by setting the txpar bit in the transmit status register. the tx_eof bit signals the end of one frame to be transmitted. when it detects this bit, the transmit block de- asserts tx_rdy until it has transmitted the packet. it then re-asserts tx_rdy when the bdma can transfer the next packet into the mac fifo. sys_clk rx_rdy rx_wr# rx_db rx_be# rx_par rx_eof ~ ~ ~ ~ ~ ~ b1 b2 b3 b1 b2 b3 ~ ~ ~ ~ b1 b2 b3 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ figure 7-17. bdi transmit data timing
S3C4530A ethernet c ontroller 7- 53 mii transmit operation the transmit block consists of three state machines: the gap_ok state machine, the back_off state machine, and the main transmit state machine. the gap_ok state machine the gap_ok state machine tracks and counts the inter-gap timing between the frames. when not operating in full-duplex mode, it counts 96 bit times from the deassertion of the carrier sense (crs) signal. if there is any traffic within the first 64 bit times, the gap_ok state machine reset itself and starts counting from zero. if there is any traffic in the last 1/3 of the inter-frame gap, the gap_ok state machine continues counting. following a successful transmission, a gap_ok is sent at the end of the next 96 bit times, regardless of the network traffic. in full-duplex mode, the gap_ok state machine starts counting at the end of the transmission and the gap_ok signal is sent at the end of the 96 bit times, regardless of the network traffic. attempt_count>= max_attempt? assemble mac frame carrier sense==on? wait for interframe gap (96-bit time), start tx with preamble + sfd collision detected? done. complete tx wait for back-off time: (=slot time x r), k = minimum (n, back-off limit (=10)) 0<=n ethernet controller S3C4530A 7- 54 the back_off state machine the back_off state machine implements the back-off and retry algorithm of the 802.3 csma/cd. when a collision is detected, the main transmit state machine starts the back_off state machine s counters and waits for the back-off time (including zero) to elapse. this time is a multiple of 512 bit times that elapse before the packet that caused the collision is re-transmitted. each time there is a collision (for one single packet), the back_off state machine increments an internal retry attempt countner. a 11-bit pseudo random number generator outputs a random number by selecting a subset of the value of the generator at any time. the subset is incremented by one bit for each subsequent attempt. this implementation is represented by the following equation: 0 =< random integer(r) < 2 k k = min (n, backoff limit (= 10)) where "r" is the number of slot times the mac must wait in case of a collision, and "n" is the number of retry attempts. for example, after the first collision, "n" is 1 and "r" is a random number between 0 and 1. the pseudo random generator in this case is one-bit wide and gives a random number of either 0 or 1. after the second attempt, "r" is a random number between 0 and 3. therefore, the state machine looks at the two least-significant bits of the random generator (n = 2), which gives a value between 0 and 3. the main transmit state machine the main transmit state machine implements the remaining mac layer protocols. if there is data to be transferred, if the inter-frame gap is valid, and if the mii is ready (that is, if there are no collisions and no crs in full-duplex mode), the transmit block then transmits the preamble followed by the sfd. after the sfd and preamble are transmitted, the block transmits 64 bytes of the data, regardless of the packet length, unless short transmission is enabled. this means that if the packet is less than 64 bytes, it will pad the llc data field with zeros. it will also appends the crc to the end of the packet, if crc generation is enabled. if there is any collision during this first 72 bytes (8 bytes of preamble and sfd, and 64 bytes of the frame), the main transmit state machine stops the transmission and transmits a jam pattern (32 bits of 1 s). it then increments the collision attempt counter, returns control to the back_off state machine, and re-transmits the packet when the back -off time has elapsed and the gap time is valid. if there are no collisions, the transmit block transmits the rest of the packet. at this time (that is, after the first 60 bytes have been transmitted without collisions), the main transmit state machine lets the bdma engine overwrite the packet. after it transmits the first 64 bytes, the transmit block transmits the rest of the packet, appending the crc to the end. parity errors, fifo errors, or more than 16 collisions will cause the transmit state machine to abort the packet (no retry) and queue up the next packet. in case of any transmission errors, the transmit block sets the appropriate error bit in the transmit status register. it may also generate an interrupt, depending on the enable bit settings in the transmit control register.
S3C4530A ethernet c ontroller 7- 55 tx_clk tx_en txd [3:0] crs ~ ~ p ~ ~ r e a m b l e ~ ~ ~ ~ ~ ~ ~ ~ col figure 7-19. timing for transmit without collision tx_clk tx_en txd [3:0] crs p1 p2 p3 p4 p5 p6 p7 p8 col j1 j2 j3 j4 figure 7-20. timing for transmit with collision in preamble
ethernet controller S3C4530A 7- 56 receiving a frame the receive block, when enabled, constantly monitors a data stream coming either from the mii or, if in loop- back mode, from the transmit block. the mii supplies from zero to seven bytes of preamble, followed by the start frame delimiter (sfd). the receive block checks that the first nibbles received are preamble, and then looks for the sfd (10101011) in the first eight bytes. if it does not detect the sfd by then, it treats the packet as a fragment and discards it. the first nibble of destination address follows the sfd, least-significant bits first. when it has received a byte, the receive block generates parity, stores the byte with its parity in the receive fifo, and asserts rx_rdy. it combines subsequent nibbles into bytes and stores them in the fifo. bdi receive data timing when the system asserts rx_rd#, the receive block reads the first byte from the fifo, checks parity, and drives the byte on rx_db, and the byte's parity on rx_par. if the fifo is now empty, it drops rx_rdy. when it drives out the last byte of a packet, it asserts rx_eof. figure 7-19 shows the timing sequence for transmitting bytes back-to-back, transmitting with wait states, and transmitting the last byte. sys_clk rx_rdy rx_rd# rx_db rx_par rx_eof ~ ~ ~ ~ ~ ~ b1 b2 b3 bn par par par par ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ figure 7-21. bdi receive data timing
S3C4530A ethernet c ontroller 7- 57 receive frame timing with/without error if, during frame reception, both rx_dv and rx_er are asserted, a crc error is reported for the current packet. as each nibble of the destination address is received, the cam block attempts to recognize it. after receiving the last destination address nibble, if the cam block rejects the packet, the receive block asserts the rx_toss signal, and discards any bytes not yet removed from the receive fifo that came from the current packet. if this operation leaves the fifo empty, it drops rx_rdy. figure 7-20 shows the mii receive data timing without error. the rx_dv signal, which entered the mii from the pcs layer, will be on when the pcs layer recovers the rx_clk from the receive bit stream and delivers the nibble data on rxd[3:0] data line. the rx_dv signal must be on before the starting frame delimiter(sfd) is received. when the rx_dv signal is on, the preamble and sfd parts of the frame header are delivered to mii, synchronized with the 25-mhz rx_clk. (the carrier sense (crs) signal was turned on during receive frame.) as its response to the rx_er signal, the mii immediately inserts an alternative data bit stream into the receive data stream. as a result, the mac discards this received error frame using the fcs. rx_clk rx_dv rxd [3:0] crs ~ ~ ~ ~ ~ ~ ~ ~ rx_er ~ ~ ~ ~ preamble sfd da sfd figure 7-22. receiving frame without error rx_clk rx_dv rxd [3:0] crs ~ ~ ~ ~ ~ ~ ~ ~ rx_er ~ ~ ~ ~ preamble sfd da sfd figure 7-23. receiving frame with error
ethernet controller S3C4530A 7- 58 carrier sense== on carrier sense = on, after detection sfd, store byte-stream in in fiso recognize address? move the byte stream in the fifo to the receive buffer memory frame too short ? frame too long? valid fcs ? interrput cpu for handing the frame mac drive software (software jobs for typical lan cards) discard the frame report error status yse no disassemble frame check ethertype or length field signal to upper layer figure 7-24. csma/cd receive operation
S3C4530A ethernet c ontroller 7- 59 the mii station manager the mdio (management data input/output) signal line is the transmit and receive path for control/status information for the station management entity, sta. the sta controls and reads the current operating status of the phy layer. the speed of transmit and receive operations is determined by the management data clock, mdc. the frame structure of the sta which writes command to control registers, or which reads the status register of a phy device, is shown table 7-45. the phy address is defined as the identification (id) value of the various phy devices that may be concected to a single mac. register addresses can contain the id value for up to 32 types of phy registers. turn-around bits are used to regulate the turn-around time of the transmit/receive direction between the sta and a phy device. so that the sta can read the set value of a phy device register, it must transmit the frame data, up to a specific register address, to the phy device. during the write time (which is an undirected transmission), the sta transmits a stream of turn-around bits. as a result, by transmitting a write or read message to a phy device through the mdio, the sta can issue a request to set the operation or to read the operation status. as its response this message, the phy device resets itself, sets loop-back mode, selects active/non-active auto- negotiation process, separates the phy and mii electrically, and determines whether or not to activate the collision detection process. when it receives a read command, the phy reports the kind of phy device it is, such as 100base-t4, fdx 100base-x, hdx 100base-x, 10-mb/s fdx, or 10-mb/s hdx. table 7-45. sta frame structure description preamble start of frame operation code phy address register address turnaround data idle write (command) 11111111 (32 bits) 01 01 (write) 5 bits 5 bits 10 (2 bits) 16 bits (register value) z read (status) 11111111 (32 bits) 01 10 (read) 5 bits 5 bits z0 16 bits (register value) z direction: sta to phy direction: phy to sta
ethernet controller S3C4530A 7- 60 full-duplex pause operations transmit pause operation to enable a full-duplex pause operation, the special broadcast address for mac control packets must be programmed into the cam, and the corresponding cam enable bit set. the special broadcast address can be a cam location. to optimize the utilization cam entries, you can specify a preference for specific cam locations. this feature is described below. the mac receive circuit recognizes a full-duplex pause operation when the following conditions are met: ? the type/length field has the special value for mac control packets, 0x8808. ? the packet is recognized by the cam. ? the length of the packet is 64 bytes. ? the operation field specifies a pause operation. when a full-duplex pause operation is recognized, the mac receive circuit loads the operand value into the pause count register. it then signals both the mac and the bdma engine that the pause should begin at the end of the current packet, if any. the pause circuit maintains the pause counter, and decrements it to zero. it does this before it signals the end of the pause operation, and before allowing the transmit circuit to resume its operation. if a second full-duplex pause operation is recognized while the first operation is in effect, the pause counter is reset with the current operand value. note that a count value of zero may cause pre-mature termination of a pause operation that is already in progress. remote pause operation to send a remote pause operation, following these steps: 1. program cam location 0 with the destination address. 2. program cam location 1 with the source address. 3. program cam location 18 with length/type field, opcode, and operand. 4. program the 2 bytes that follow the operand with 0000h. 5. program the three double words that follow cam location 18 with zeros. 6. write the transmit control register to set the sdpause bit. the destination address and source address are commonly used as the special broadcast address for mac control frames and the local station address, respectively. to support future uses of mac control frames, these values are fully programmable in the flow control 100-/10-mbit/s ethernet mac. when the remote pause operation is completion, the transmit status is written to the transmit control frame status register. the bdma engine is responsible for providing an interrupt enable control.
S3C4530A ethernet c ontroller 7- 61 error signalling the error/abnormal operation flags asserted by the mac are arranged into transmit and receive groups. these flag groups are located either in the transmit status register (tx_stat) or the receive status register (rx_stat). a missed packet error counter is included for system network management purposes. normally, software does not have enough direct control to examine the status registers directly. therefore, the bdma engine must store the values in system memory so that they can be examined there by software. reporting of transmission errors a transmit operation terminates when the entire packet (preamble, sfd, data, and crc) has been successfully transmitted through the mii without a collision. in addition, the transmit block detects and reports both internal and network errors. under the following conditions, the transmit operation will be aborted (in most cases). parity error the 8 bits of data coming in through the bdii has an optional parity bit. a parity bit also protects each byte in the mac transmit fifo. if a parity error occurs, it is reported to the transmit state mach ine, and the transmission is aborted. a detected parity error sets the txpar bit in the transmit status register. transmit fifo underrun the 80-byte transmit fifo can handle a system latency of 6.4bi (640 bit times). an underrun of the transmit fifo during transmission indicates a system problem (namely, that the system cannot keep up with the demands of the mac), and the transmission is aborted. no crs the carrier sense signal (crs) is monitored from the beginning of the start of frame delimiter (sfd) to the last byte transmitted. a "no crs" indicates that crs was never present during transmission (a possible network problem), but the ransmission will not be aborted. note that during loop-back mode, the mac is disconnected from the network, and a "no crc" will not be detected. excessive collision error whenever the mac encounters a collision during transmit, it will back off, update the "attempt counter," and retry the transmission later on. when the attempt counter rea ches 16 (16 attempts that all resulted in a collision), the transmission is aborted. this indicates a network problem. late collision error (transmit out of window collision) normally, the mac would detect a collision (if one occurs) within the first 64 bytes of data that are transmitted, including the preamble and sfd. if a collision occurs after this time frame, a possible network problem is indicated. the error is reported to the transmit state machine, but the transmission is not aborted . instead, it performs a back-off, as usual. excessive deferral error during its first attempt to send a packet, the mac may have to defer the transmission because the network is busy. if this deferral time is longer than 32k bit times, the transmission is aborted. excessive deferral errors indicate a possible network problem.
ethernet controller S3C4530A 7- 62 reporting of receive errors when it detects a start of frame delimiter (sfd), the receive state machine starts putting data it has received from the mii into the receive fifo. it also checks for internal errors (fifo overruns) while reception is in progress. when the receive operation is completed, the receive state machine checks for external errors, such as frame alignment, length, crc, and frame too long. the following is a description of the types of errors that may occur during a receive operation: priority error a parity bit protects each byte in the mac receive fifo. if a parity error occurs, it is reported to the receive state machine. a detected parity error s ets the rxpar bit in the receive status register. frame alignment error (dribble) after receiving a packet, the receive block checks that the incoming packet (including crc) was correctly framed on an 8-bit boundary. if it is not and if the crc is invalid, data has been disrupted through the network, and the receive block reports a frame alignment error. a crc error is also reported. crc error after receiving a packet, the receive block checks the crc for validity, and reports a crc error if it is invalid. the receive unit can detect network-related errors such as crc, frame alignment, and length errors. it can also detect these types of errors in the following combinations: ? crc errors only ? frame alignment and crc errors only ? length and crc errors only ? frame alignment, length, and crc errors frame too long the receive block checks the length of the incoming packet at the end of reception (including crc, but excluding preamble and sfd). if the length is l onger than the maximum frame size of 1518 bytes, the receive block reports receiving a "long packet", unless long frame mode is enabled. receive fifo overrun during reception, the incoming data are put into the receive fifo temporarily before they are transferred to the system memory. if the fifo is filled up because of excessive system latency or for other reasons, the receive block sets the overrun bit in the receive status register. mii error the phy informs the mac if it detects a medium error ( such as a coding violation) by asserting the input pin rx_er. when the mac sees rx_er asserted, it sets crcerr bit of the receive status register.
S3C4530A ethernet c ontroller 7- 63 timing parameters for mii transactions the timing diagrams in this section conform to the guidelines described in the "draft supplement to ansi/ieee std. 802.3, section 22.3, signal characteristics." tx_clk txd[3:0] tx_en output valid 4.9ns min 28ns min figure 7-25. transmit signal timing relationship at mii rx_clk rxd[3:0] rx_dv th : 5ns ts : 3ns input valid figure 7-26. receive signal timing relationship at mii mdc mdio input valid ts : 15ns figure 7-27. mdio sourced by phy mdc mdio output valid th : 13ns figure 7-28. mdio sourced by sta
ethernet controller S3C4530A 7- 64 mac controller 7-wire interface timing table 7-46. 7-wire interface receive timing symbol condition min typ max unit ts_crs crs low to high setup time 0.92 ns th_crs crs low to high hold time 0.38 ns ts_dv rx_dv set-up time 0.9 ns th_dv rx_dv hold time 0.4 ns ts_d rxd set-up time 0.79 ns th_d rxd hold time 0.51 ns ts_er rx_er set-up time 0.9 ns th_er rx_er hold time 0.4 ns tcyc rx_clk clock period 100 ns rx_clk rx_dv rxd crs rx_er th_crs ts_crs preamble sfd crc tcyc da th_dv ts_dv th_d ts_d th_er ts_er figure 7-29. rx timing in 7 wire interface
S3C4530A ethernet c ontroller 7- 65 table 7-47. 7-wire interface transmit timing symbol condition min typ max unit ts_en tx_en set-up time 0.8 ns th_en tx_en hold time 0.71 ns ts_crs crs set-up time 0.72 ns th_crs crs hold time 0.75 ns ts_d txd set-up time 1.2 ns th_d txd hold time 0.5 ns ts_col col set-up time 0.82 ns th_col col hold time 0.79 ns tcol col minimum active time 200 ns tx_clk tx_en txd crs th_cn th_col ts_en ts_col th_crs ts_crs th_d ts_d col tcol figure 7-30. tx timing in 7 wire interface
ethernet controller S3C4530A 7- 66 notes
S3C4530A hdlc contr ollers 8- 1 8 hdlc controllers overview the S3C4530A has two high-level data link controllers (hdlcs) to support two-channel serial communications. the hdlc module supports a cpu/data link interface that conforms to the synchronous data link control (sdlc) and high-level data link control (hdlc) standards. in addition, the following function blocks are integrated into the hdlc module: ? two-channel dma engine for tx/rx ? support buffer descriptors per frame ? digital phase-locked loop (dpll) block ? baud rate generator (brg)
hdlc controllers s3 c4530a 8 - 2 features important features of the S3C4530A hdlc block are as follows: ? protocol features: flag detection and synchronization zero insertion and deletion idle detection and transmission fcs encoding and detection (16-bit) transparent mode support time slot assignor support (tsa) abort detection and transmission ? four address station registers and one mask register for address search mode ? selectable crc/no-crc mode ? automatic crc generator pre-set ? digital pll block for clock recovery ? baud rate generator ? nrz/nrzi/fm/manchester data formats for tx/rx ? loop-back and auto-echo mode ? tx and rx fifos with 8-word (8 x 32-bit) depth ? selectable 1-word or 4-word data transfer mode for tx/rx ? data alignment logic ? endian translat ion ? programmable interrupts ? modem interface ? hardware flow control ? buffer descriptor for tx / rx ? two-channel dma controller two channels for htxfifo and hrxfifo single or 4-word (4 x 32-bit) burst transfer mode maximum frame size allows for up to 64k bytes ? up to 10 mbps full-duplex operation using an external/internal clock ? hdlc frame length based on octets
S3C4530A hdlc contr ollers 8- 3 function descriptions figure 8-1 shows the hdlc module's function blocks. these function blocks are described in detail in the following sections. dma controlller address bus arbiter/ controller address data control tx fifo (8 words) flag/abort/idle generateor and transmitter receive shift register rx fifo (8 words) fcs generator zero insertion flag/abort/idle detection zero delection loop dpll dplloutr dplloutt rxd txc txd autoecho rxc mclk2 (= 25 mhz) brgout1 brgout2 word system bus hdlc control and status registers fcs checker encoder decoder remote serial port brg figure 8-1. hdlc module block diagram
hdlc controllers s3 c4530a 8 - 4 hdlc frame format the hdlc transmits and receives data (address, control, information and crc field) in a standard format called a frame. all frames start with an opening flag (beginning of flag, bof, 7eh) and end with a closing flag (end of flag, eof, 7eh). between the opening and the closing flags, a frame contains an address (a) field, a control (c) field, an information (i) field (optional), and a frame check sequence (fcs) field (see table 8-1). table 8-1. hdlc data frame format opening flag address field control field information field frame check sequence field closing flag 01111110 8 bits per byte 8 bits per byte 8 bits per byte; variable length 16 bits 01111110 note : the address field can be extended up to four bytes using a optional software control setting. flag (f) a flag is a unique binary pattern (01111110) that is used to delimit hdlc frames. this pattern is generated internally by the transmitter. an opening flag starts a frame and a closing flag ends the frame. opening flags and closing flags are automatically appended to frames. a single flag pattern can optionally serve as both the closing flag of one frame and the opening flag of the next one. this feature is controlled by the double-flag (ff), single-flag (f), or frame separator selection bit (the txsdfl bit in the hcon register). order of bit transmission address field, control field, and information field bytes are transferred between the cpu and the hdlc module in parallel over the data bus. these bytes are transmitted and received lsb first. the 16-bit frame check sequence (fcs) field is, however, transmitted and received msb first.
S3C4530A hdlc contr ollers 8- 5 address (a) field the eight bits that follow the opening flag are called address (a) field. the address field are expendable. to extend this address byte, simply user-defined address write to the station address register. to check address byte against the incoming data, have to be used the mask register. if match occurred, the frame's data including address and crc(16-bit) into the hrxfifo and then moved to system memory. if it is not matched, simply discarded. S3C4530A allows up to 32-bits address. for instance, sdlc and lapb use an 8-bit address. lapd further divides its 16-bit address into different fields to specify various access points one piece of equipment. some hdlc-type protocol allows for extended addressing beyond 16-bit. control (c) field the eight bits that follow the address field are called the control (link control, c) field. the S3C4530A hdlc module treats the control field in the same way as the information field. that is, it passes the eight bits to the cpu or memory during reception. the cpu is responsible for how the control field is handled and what happens to it. information (i) field the information (i) field follows the control (c) field and precedes the frame check sequence (fcs) field. the information field contains the data to be transferred. not every frame, however, must actually contain information data. the word length of the i-field is eight bits in the S3C4530A hdlc module. and its total length can be extended by 8 bits until terminated by the fcs field and the closing flag. frame check sequence (fcs) field the 16 bits that precede the closing flag comprise the frame check sequence (fcs) field. the fcs field contains the cyclic redundancy check character, crcc. the polynomial x16 + x12 + x5 + 1 is used both for the transmitter and the receiver. both the transmitter and the receiver polynomial registers are all initialized to 1 prior to calculating of the fcs. the transmitter calculates the frame check sequence of all address bits, control bits, and information fields. it then transmits the complement of the resulting remainder as the fcs value. the receiver performs a similar calculation for all address, control, and information bits, as well as for all the fcs fields received. it then compares the result to f0b8h. when a match occurs, the frame valid (rxfv) status bit is set to '1'. when the result does not match, the receiver sets the crc error bit (rxcrce) to '1'. the transmitter and the receiver automatically perform these fcs generation, transmission and checking functions. the S3C4530A hdlc module also supports no crc operation mode. in no crc mode, transmitter does not append fcs to the end of data and the receiver also does not check fcs. in this mode, the data preceding the closing flag is transferred to the hrxfifo. in crc mode, the fcs field is transferred to the hrxfifo.
hdlc controllers s3 c4530a 8 - 6 protocol features invalid frame a valid frame must have at least the a, c, and fcs fields between its opening and closing flags. even if no-crc mode is set, the frame size should not be less than 32 bits. there are three invalid frame conditions: short frame: a frame that contains less than 25 bits between flags. short frames are ignored. invalid frame: a frame with 25 bits or more, having a crc compare error or non- byte-aligned. invalid frames are transferred to the hrxfifo, then the invalid frame error flag (rxcrce, rxno in the status register) is set to indicate that an invalid frame has been received. aborted frame: a frame aborted by the reception of an abort sequence is handled as an invalid frame. zero insertion and zero deletion the zero insertion and zero deletion feature, which allows the content of a frame to be transparent, is handled automatically by the hdlc module. while the transmitter inserts a binary '0' following any sequence of five 1s within a frame, the receiver deletes a binary '0' that follows a sequence of five 1s within a frame. abort the function of early termination of a data link is called an abort the transmitter aborts a frame by sending at least eight consecutive 1s immediately after the abort transmitter control bit (txabt in hcon) is set to '1'. (setting this control bit automatically clears the htxfifo.) the abort sequence can be extended up to (at least) 16 consecutive 1s by setting the abort extend control bit (txabtext in hcon) to '1'. this feature is useful for forcing the mark idle state. the receiver interprets the reception of seven or more consecutive 1s as an abort. the receiver responds the abort received as follows: an abort in an 'out of frame' condition: an abort has no meaning during the idle or the time fill an abort 'in frame' after less than 25 bits are received after an opening flag: under this condition, no field of the aborted frame is transferred to the hrxfifo. the hdlc module clears the aborted frame data in the receiver and flag synchronization. the aborted reception is indicated in the status register. an abort 'in frame' after 25 bits or more are received after an opening flag: in this condition, some fields of the aborted frame may be transferred to the hrxfifo. the abort status is set in the status register and the data of the aborted frame in the hrxfifo is cleared. flag synchronization is also cleared and the dma operation for receiving is aborted too. idle and time fill when the transmitter is not transmitting a frame, it is in an idle state. the transmitter signals that it has entered an idle state in one of the following two ways: 1) by transmitting a continuous series of flag patterns (time fill), or 2) by transmitting a stream of consecutive 1s (mark idle). the flags and mark idle are not transferred to the hrxfifo. the flag or mark idle selection bit (txflag in hcon) controls this function: when txflag is '0', mark idle is selected; when txflagidle is '1', the time fill method is selected.
S3C4530A hdlc contr ollers 8- 7 fifo structure in both transmit and receive directions, 32-byte(8 word) deep fifos are provided for the intermediate storage of data between the serial interface and the cpu interface. two-channel dma engine the hdlc module has a two-channel dma engine for tx/rx fifos. the dma tx channel programming and the rx channel programming are described in the transmitter and receiver operation sections, respectively. baud rate generator the hdlc module contains a programmable baud rate generator(brg). the brg register contains a 16-bit time constant register, a 12-bit down counter for time constant value, two control bit to divide 16, and another two control bits to divide 16 or 32. a clock diagram of the brg is shown in figure 8-2. at a start-up, the flip-flop on the output is set in a high state, the value in the time constant register is loaded into the counter, and the counter starts counting down. the output of the baud rate generator may toggle upon reaching zero, the value in the time constant register is loaded into the counter, and the process is repeated. the time constant may be changed any time, but the new value does not take effect until the next load of the counter. the output of the baud rate generator may be used as either the transmit clock, the receive clock, or both. it can also drive the digital phase-locked loop. if the receive or transmit clock is not programmed to come from the txc pin, the output of the baud rate generator may be echoed out via the txc pin. the following formula relates the time constant to the baud rate where mclk2 or rxc is the baud rate generator input frequency in hz. brg generates 2 output signals, brgout1, brgout2, for transmit/receive clocks and the dpll input clock. brgout1 = (mclk2 or rxc) / (cnt0 + 1) / (16 cnt1 ) brgout2 = brgout1 / (1 or 16 or 32 according to cnt2 value of the hbrgtc) brgout2 12-bit counter cnt0 brgclk divide by 1 or 16 cnt1 divide by 1 or 16 or 32 cnt2 rxc mclk2 brgout1 cnt0: hbrgtc [15:4] cnt1: hbrgtc [3:2] cnt2: hbrgtc [1:0] brgclk: hmode [19] figure 8-2. baud rate generator block diagram the example in the following table assumes a 25mhz clock from mclk2, a 24.576mhz clock from rxc, showing a time constant for a number of commonly used baud rates .
hdlc controllers s3 c4530a 8 - 8 table 8-2. baud rate example of hdlc baud rate mclk = 25 mhz r c = 24.576 mhz (brgout2) cnt0 cnt1 cnt2 freq. dev. (%) cnt0 cnt1 cnt2 freq. dev. (%) 1200 1301 0 1 1200.1 0.0 1279 0 1 1200.0 0.0 2400 650 0 1 2400.2 0.0 639 0 1 2400.0 0.0 4800 324 0 1 4807.7 0.2 319 0 1 4800.0 0.0 9600 162 0 1 9585.9 -0.1 159 0 1 9600.0 0.0 19200 80 0 1 19290.1 0.5 79 0 1 19200.0 0.0 38400 40 0 1 38109.8 -0.8 39 0 1 38400.0 0.0 57600 26 0 1 57870.4 0.5 26 0 1 56888.9 -1.2 115200 13 0 1 111607.1 -3.1 12 0 1 118153.8 2.6
S3C4530A hdlc contr ollers 8- 9 digital phase-locked loop (dpll) the hdlc module contains a digital phase-locked loop (dpll) function to recover clock information from a data stream with nrzi or fm encoding. the dpll is driven by a clock that is normally 32 (nrzi) or 16 (fm) times the data rate. the dpll uses this clock, along with the data stream, to construct the clock. this clock may then be used as the receive clock, the transmit clock, or both. figure 8-3 shows a block diagram of the digital phase-locked loop. it consists of a 5-bit counter, an edge detector and a pair of output decoders. edge detector count modifier decoder receive clock dplloutr hmode[18:16] 5-bit counter decoder transmit clock dplloutt rxd txc rxc mclk brgout1 brgout2 figure 8-3. dpll block diagram clock usage method note: brgclk = hmode [19] dpllclk = hmode [18:16] txclk = hmode [22:20] rxclk = hmode [26:24] dplloutt dpllortr dpll txc rxc mclk brgout1 brgout2 dpllclk brgout1 brgout2 baud rate generator brgclk rxc mclk2 transmit data transmit clock txc rxc dplloutt brgout1 brgout2 transmitter txclk receive data receive clock txc rxc dplloutt brgout1 brgout2 receiver rxclk figure 8-4. clock usage method diagram
hdlc controllers s3 c4530a 8 - 10 in the nrz/nrzi mode, the dpll source clock must be 32 times the data rates. in this mode, the transmit and receive clock outputs of the dpll are identical, and the clocks are phased so that the receiver samples the data in the middle of the bit cell. the dpll counts the 32x clock using an internal 5-bit counter. as the 32x clock is counted, the dpll searches the incoming data stream for edges (either positive or negative transition). the output of dpll is high while the dpll is waiting for an edge in the incoming data stream. when it detects a transition, the dpll starts the clock recovery operation. the first sampling edge of the dpll occurs at the counter value of 16 after the first edge is detected in the incoming data stream. the second sampling edge occurs following the next 16. when the transition of incoming data occurs at a count value other than 16, the dpll adjusts its clock outputs during the next 0 to 31 counting cycle by extending or shortening its count by one, which effectively moves the edge of the clock sampling the receive data closer to the center of the bit cell. the adding or subtracting of a count of 1 will produce a phase jitter of 5.63 degrees on the output. because the dpll uses both edges of the incoming signal for its clock source comparison, the mark-space ratio (50%) of the incoming signal must not deviate more than 1.5% of its baud rate if proper locking is to occur. in the fm mode, the dpll clock must be 16 times the data rate. the 5-bit counter in the dpll counts from 0 to 31, so the dpll makes two sampling clocks during the 0 to 31 counting cycle. the dpll output is low while the dpll is waiting for an edge in the incoming data stream. the first edge the dpll detects is assumed to be a valid clock edge. from this point, the dpll begins to generate output clocks. in this mode, the transmit clock output of the dpll lags the receive clock outputs by 90 degrees to make the transmit and receive bit cell boundaries the same, because the receiver must sample the fm data at a one- quarter and three-quarters bit time. you can program the 32x clock for the dpll to originate from one of the rxc input pins, from the txc pin, or from the baud rate generator output. you can also program the dpll output to be "echoed out" of the hdlc module over the txc pin(if the txc pin is not being used as an input). during idle time, you can set the txprmb in hcon to send the special pattern required for a remote dpll to lock the phase. in this case, the content of the hprmb register is sent repeatedly. the length of preamble is determined by txpl bit in hmode[10:8]. it is noticed that the frequency of the receive clock (rxc) should be slower than half of the internal system clock i.e., mclk/2. otherwise, the data transfer from receive fifo to memory could be lost.
S3C4530A hdlc contr ollers 8- 11 hdlc operational description the following sections describe the operation of the hdlc module. hdlc initialization a power-on or reset operation initializes the hdlc module and forces it into the reset state. after a reset, the cpu must write a minimum set of registers, as well as any options set, based on the features and operating modes required. first, the configuration of the serial port and the clock mode must be defined. these settings include the following: ? data format select ? brg clock select ? dpll clock select ? transmit clock select ? receive clock select ? brg/dpll enable to use internal clock you must also set the clock for various components before each component is enabled. additional registers may also have to be programmed, depending on the features you select. all settings for the hdlc mode register, hmode, and the hdlc control register, hcon, must be programmed before the hdlc is enabled. to enable the hdlc module, you must write a '1' to the receiver enable bit and/or the transmitter enable bit. during normal operation, you can disable the receiver or the transmitter by writing a '0' to the rxen or txen bit, respectively. you can disable the receiver and hrxfifo or the transmitter and htxfifo by writing a '1' to the rxrs or txrs bit, respectively.
hdlc controllers s3 c4530a 8 - 12 hdlc data encoding/decoding data encoding is used to allow the transmission of clock and data information over the same medium. this saves the need to transmit clocks and data over a separate medium as would normally be required for synchronous data. the hdlc provides four different data encoding methods, selected by bits in hcon1[18:16]. an example of these four encoding methods is shown in figure 8-5. 1 1 0 0 1 0 data nrz nrzi fm1 (biphase mark) fm0 (biphase space) manchester nrz, nrzi type txclock data rxclock fm0/fm1/manchester type txclock data rxclock note: transmit clock and receive clock can be controlled by softwear using hmode[3:2] register. this t iming diagram is one example of hmode[3:2] bit value set to '00'. hmode[2]: rx clock inversion bit (rxcinv) hmo de[3]: tx clock inversion bit (txcinv) bit cell level: high = 1 low = 0 no change = 1 change = 0 bit center transition: transition = 1 no transition = 0 no transition = 1 transition = 0 high low = 1 low high = 0 figure 8-5. data encoding methods and timing diagrams
S3C4530A hdlc contr ollers 8- 13 hdlc transmitter operation the htxfifo register cannot be pre-loaded when the transmitter is disabled. after the hdlc tx is enabled, the flag or mark idle control bit (txflag in hcon) is used to select either the mark idle state (inactive idle) or the flag 'time fill' (active idle) state. this active or inactive idle state will continue until data is loaded into the htxfifo. the content of the hprmb register can be sent out by setting the txprmb in hcon for the remote dpll before the data is loaded into the htxfifo. the length of preamble to be transmitted is determined by txpl bits in hmode. the availability of data in the htxfifo is indicated by the htxfifo available bit (txfa in hstat) under the control of the 4-word transfer mode bit (tx4wd in hcon). when you select 1-word transfer mode (not 4-word select mode), one word can be loaded into the htxfifo (assuming the txfa bit is set to '1'). when you select 4-word transfer mode, four successive words can be transferred to the fifo if the txfa bit is set to '1'. the ncts (clear-to-send) input, nrts (request-to-send), and ndcd (data-carrier-detect) are provided for a modem or other hardware peripheral interface. in auto enable mode, ncts becomes the transmitter enable. however, the transmitter enable bit must be set before the ncts pin is used in this manner. when the autoen is "0" and there are data to transmit, the transmitter enforces nrts pin to go "low" and starts to send the data from txfifo. when the autoen is "1" and there are data to transmit, the transmitter must wait ncts pin "low" before transmission. the txfc status bit(in hstat) can cause an interrupt to be generated upon frame completion (this bit is set when there is no data in htxfifo and when the closing flag or an abort is transmitted).
hdlc controllers s3 c4530a 8 - 14 transmitter interrupt mode the first byte of a frame (the address field) should be written into the tx fifo at the 'frame continue' address. then, the transmission of the frame data starts automatically. the bytes of the frame continue to be written into the tx fifo as long as data is written to the 'frame continue' address. the hdlc logic keeps track of the field sequence within the frame. the frame is terminated when the last frame data is written to the tx fifo's 'frame terminate' address. the fcs field is automatically appended by hardware, along with a closing flag. data for a new frame can be loaded into the tx fifo immediately after the previous frame data, if txfa is '1'. the closing flag can serve as the opening flag of the next frame or separate opening and closing flags can be transmitted. if a new frame is not ready to be transmitted, a flag time fill or mark idle pattern is transmitted automatically. if the tx fifo becomes empty at any time during the frame transmission, an under-run occurs and the transmitter automatically terminates the frame by transmitting an abort. the under-run state is indicated when the transmitter under-run status bit (txu) is '1'. whenever you set the transmission abort control bit (txabt in hcon), the transmitter immediately aborts the frame (transmits at least eight consecutive 1s), clearing the tx fifo. if the transmission abort extension control bit (txabtext) is set at the time, an idle pattern (at least 16 consecutive 1s) is transmitted. an abort or idle in an out- of-frame condition can be useful to gain 8 or 16 bits of delay time between read and write operations. transmitter dma mode to use dma operation without cpu intervention, you have to make tx buffer descriptor chain in advance. and set the dma tx buffer descriptor pointer(dmatxptr) register to the address of the first buffer descriptor of the chain, and then dma tx channel should be enabled. when tx under-run or cts lost condition occurs during dma operation, dma tx enable bit(hcon[6]) is cleared and dma tx operation is stopped. this situation is reported to system with dtxabt bit set(hstat[22]). in case of tx under-run, abort signal sent and then dtxeen bit cleared automatically. in case of cts lost, txd output goes high state as long as ncts remains high level when auto enable bit set to one .
S3C4530A hdlc contr ollers 8- 15 hdlc receiver operation the hdlc receiver is provided with data and a pre-synchronized clock by means of the rxd and the internal dpll clock, the txc pin, or the rxc pin. the data is a continuous stream of binary bits. one of the characteristics of this bit stream is that a maximum of five consecutive 1s can occur unless an abort, flag, or idle condition occurs. the receiver continuously searches (bit-by-bit) for flags and aborts. when a flag is detected, the receiver synchronizes the frame to the flag timing. if a series of flags is received, the receiver re-synchronizes the frame to each successive flag. if the frame is terminated because of a short frame condition (frame data is less than 32 bits after an opening flag), the frame is simply ignored. noise on the data input line (rxd) during time fill can cause this kind of invalid frame. the received data which is clocked by the external txc or rxc, or by an internal dpll or brg source enters a 56-bit or 32-bit shift register before it is transferred into the hrxfifo. synchronization is established when a flag is detected in the first eight locations of the shift register. when synchronization has been achieved, data is clocked through to the last byte location of the shift register where it is transferred into the hrxfifo. in 1-word transfer mode, when the hrxfifo available bit (rxfa) is '1', data is available at least in one-word. in 4-word transfer mode, the rxfa is '1' when data is available in the last four fifo register locations (registers 4, 5, 6, and 7). the ndcd input is provided for a modem or other hardware interface. if autoen bit in hcon[28] is set to '1', the receiver operation is dependent on the ndcd input level. otherwise, receiver operation is free of the ndcd input level. receiver interrupt mode whenever data is available in the hrxfifo, an interrupt is generated by rxfa (if the interrupt is enabled). the cpu reads the hdlc status register either in response to the interrupt request or in turn during a polling sequence. when the received data available bit (rxfa) is '1', the cpu can read the data from the hrxfifo. if the cpu reads normal data or address data from the hrxfifo, the rxfa bit is automatically cleared. in crc mode, the 16 bits preceding the closing flag are regarded as the fcs and checked by hardware, and they are transferred to the hrxfifo. also, in no crc mode, without the hardware checking, all data bits preceding the closing flag are transferred to the hrxfifo. when the closing flag is sent to the receiver, the frame is terminated. whatever data is present in the most significant byte of the receiver, the shift register is right justified and transferred to the hrxfifo. the frame boundary pointer, which is explained in the hrxfifo register section, is set simultaneously in the hrxfifo. when the last byte of the frame appears at the 1-word or 4-word boundary location of the hrxfifo, depending on the settings of the rx4wd control bit, the frame boundary pointer sets the frame valid status bit (if the frame is completed with no error) or the rxcrce status bit(if the frame was completed, but with a crc error). if the frame reception is completed, an rxcrce interrupt (for a frame error) or an rxfv interrupt (for normal state) is generated. at this point, the cpu can read the rx remaining bytes (rxrb) status bits to know how many bytes of this frame still remain in the hrxfifo. when you set the frame discontinue control bit (the incoming frame discard control bit) to '1', the receiver discards the current frame data without dropping the flag synchronization. you can use this feature to ignore a frame with a non-matched address.
hdlc controllers s3 c4530a 8 - 16 receiver dma mode to use dma operation without cpu intervention, you have to make rx buffer descriptor chain in advance. and set the dma rx buffer descriptor pointer(dmarxptr) register to the address of the first buffer descriptor of the chain, and then dma rx channel should be enabled. hardware flow control last txclock txd rts cts figure 8-6. ncts already asserted when ncts is active and there exists data to be transmitted in tx fifo, nrts enters low, allowing data transmission. at the beginning of the data is an open flag while at the end a closing flag. if the frame being transferred discontinues, nrts goes back to the high after the data transmission is completed. txclock txd rts cts data 14 - 22 cycles 5-13 cycles figure 8-7. cts lost during transmission when the condition of ncts is shifted from low to high, it is detected at the falling edge of tx clock, where nrts also goes high. for about 5 to 13 cycles after nrts enters high, the data transmission continues. nrts remains high for a maximum of 22 cycles and goes back to the low condition if there remains any data to be transmitted in htxfifo. if ncts is still high even when nrts went back to low, not the data in htxfifo but a mark idle pattern is transmitted when autoen bit set to one.
S3C4530A hdlc contr ollers 8- 17 txclock txd rts cts data 14 - 22 cycles figure 8-8. cts delayed on if ncts remains still high for a while after nrts enters low to allow data transmission from htxfifo, the data transmission starts 5-12 cycles after ncts is shifted to low.
hdlc controllers s3 c4530a 8 - 18 transparent operation the S3C4530A can transmit or receive the data from the cpu without any modification in the transparent mode. in this mode, no protocol conversion such as zero insertion/deletion, flag insertion/detection, abort transmission/detection in hdlc frame is performed by the hardware. instead, any protocol can be implemented on the transmission channel by the software. the S3C4530A performs simply a serial-to-parallel and parallel-to- serial conversion. transparent transmitter operation the transmitter enters transparent mode by setting txtrans to "1" in hmode. the transmitter starts to send "1" in idle state. when the autoen is "0" and there are data to transmit, the transmitter enforces nrts pin to go "low" and starts to send the data from txfifo. when the autoen is "1" and there are data to transmit, the transmitter must wait ncts pin "low" before transmission. once these conditions are met, the transmission will be started. when the last byte sent from txfifo, the transmitter sends "1" after last byte transmission. if the txrev in hcon is set to "1", each data byte will be reversed in its bit order before transmission (msb first transmitted). transparent receiver operation the receiver enters in transparent mode by setting rxtrans to "1" in hmode. in this mode, the receiver waits to gain synchronization before receiving data. once the reception begins, the receiver moves the data from rxd pin to rxfifo. the receiver will not stop receiving data until the trxstop in hcon is set to "1", which makes the rceiver to stop receiving and to go to wait synchroniztion again. if the rxrev in hcon is set to "1", each data byte will be reversed in its bit order before entering rxfifo (msb first received). transparent synchronization the S3C4530A must be synchronized before transmitting or receiving data. the synchronization method is selectable by software control. the transmitter achieves synchornization by monitoring ncts pin depending on autoen in hcon. if autoen is "0", the transmitter is allowed to transmit data anytime there are data in txfifo. however, if autoen is "1", the transmitter can start transmission only when the state of ncts pin is "low". the receiver can be synchronized two ways. when autoen is "0" and the receiver is transparent mode, the receiver searches the rxd for the pattern in hsync register. once the pattern in hsync content is detected on the rxd, the data reception will be started. this synchronization method is inline-synchronization. another synchronization is achieved when autoen is "1" and the receiver is transparent mode. in this condition, the receiver monitors dcd pin to find a negative transition and then starts to receive data from rxd. once the data reception begins, the transition of dcd pin will be ignored and data can be received until trxstop is set to one by cpu then the new synchronization process begins. this synchronization method is external synchronization. if the trxstop in hcon is set to "1", the receiver stops data reception and goes to wait synchronization again.
S3C4530A hdlc contr ollers 8- 19 tsa (time slot assigner) the S3C4530A includes one time-slot-assignor (tsa), which provides flexible data path control between the two hdlcs and external interfaces. two types of data interface can be supported by the S3C4530A with the tsa: data communication equipment (dce), pulse code modulation (pcm) highway (non-multiplexed mode and multiplexed mode). each tsa can be programmed to select one between dce and pcm highway (non-multiplexed) interface. in dce interface, the internal hdlc can directly be connected to the external serial interface. in pcm highway interface, the tsa is located between the hdlc and the external serial interface. by intervening in-between, the tsa provides the appropriate hdlc clocks during its programmed timeslot within an 8-khz frame. the tsa can support a maximum data rate up to 10mbps with hdlcs. in pcm highway interface, up to 156 time-slots can be supported with credible data transfer. although the S3C4530A can support up to 4096 bit positions (12-bit programmable), this requires a lower frequency of fsc or a high frequency of clock rates. the pcm highway (multiplexed) is pin-multiplexed with hdlca pin interface and the hdlcb pins are dedicated to dce interface. hdlca hdlcb mux dcea tdm dceb dce/iom2 interface dce interface tsa tdma tdmb figure 8-9. tsa block diagram
hdlc controllers s3 c4530a 8 - 20 hdlc external pin multiplexed signals hdlc external pins are multiplexed among the operating mode. the mode bits in tsacfg determines the operating mode of each tsa and hdlc external pins are automatically configured according to mode bits as follows. table 8-3. hdlc external pin multiplexed signals channel external interface default signal dce pcm a dce_txca pcm_fsc dce_txca dce_txda pcm_txd dce_txda dce_rxca pcm_dcl dce_rxca dce_rxda pcm_rxd dce_rxda b dce_txcb - dce_txcb dce_txdb - dce_txdb dce_rxcb - dce_rxcb dce_rxdb - dce_rxdb operation the time slot assignor (tsa) controllers are configured as follows: 1. configure the tsacfg register. ? define the start bit position for each tsa. ? define the stop bit position for each tsa. ? determine operating mode for each tsa (dce, pcm highway (non-multiplexed or multiplexed). 2. enable tsa by setting tsaen bit in tsacfg[0] to "1". 3. program each intended hdlc channel clock divide in pcm mode, the tsa provides each hdlc channel with proper clock according to its programmed timeslot. in this process, the clock frequency is either the same as or 1/2 times that of the external clock. when the divide bit in tsaxcfg[3] is set to "1", each hdlc channel is provided with half frequency clock of external clock and the tx data is shifted out every two external clock. when the divide bit in tsaxcfg[3] is "0", each hdlc channel is provided with the external clock and the tx data is shifted out every one clock.
S3C4530A hdlc contr ollers 8- 21 memory data structure the flow control to the hdlc controller uses two data structures to exchange control information and data. ? transmit buffer descriptor ? receive buffer descriptor each tx dma buffer descriptor has the following elements. ? buffer data pointer ? ownership bit ? control field for transmitter ? status field for tx ? transmit buffer length ? next buffer descriptor pointer each rx dma buffer descriptor has the following elements. ? buffer data pointer ? ownership bit ? status field for rx ? accumulated received buffer length for a frame ? next buffer descriptor pointer
hdlc controllers s3 c4530a 8 - 22 data buffer descriptor the ownership bit in the msb of the buffer data pointer controls the ownership of the descriptor. when the ownership bit is '1', the dma controller owns the descriptor. when this bit is '0', the cpu has the descriptor. the owner of the descriptor always owns the associated data frame. (the descriptor's buffer data pointer field always points to this buffer for about a frame.) as it receives the data, the software sets the maximum frame length register. if the received data is longer than the value of the maximum frame length register, this frame is ignored and the flv bit is set. the software also sets the dma rx buffer descriptor pointer to point to a chain of buffer descriptors, all of which have their ownership bit. the dma controller can be started to set the dma rx enable bit in the control register. when a frame is received, it is moved into memory at the address specified by the dma rx data buffer pointer. if a frame is longer than the value of the rxbufsize register, then the next buffer descriptors are fetched to receive the frame. that is, to handle a frame, one or more buffer descriptors could be used. please note that no configurable offset or page boundary calculation is required. the received frame is moved to the buffer memory whose address is pointed to by the buffer data pointer until the end of frame, or until the length exceeds the maximum frame length configured. if the length exceeds the maximum frame length configured, the frame length violated bit is set. if the entire frame is received successfully, the status bits in the receive buffer descriptor are set to indicate the received frame status. the ownership bit in the buffer descriptor pointer is cleared by the cpu which has the ownership and an interrupt may now be generated. the dma controller copies the next buffer descriptor pointer into the dma rx buffer descriptor pointer register. if the next buffer descriptor pointer is null(0), the drxen bit is cleared, and dma rx operation is stopped. otherwise, the descriptor is read, and the dma controller starts again with the next data, as described in the previous paragraph. when the dma reads a descriptor, if the ownership bit is not set, it has two options: skip to the next buffer descriptor when drxstsk bit is '0' generate an interrupt and halt the dma operation when drxstsk bit is '1' during transmission, the two-byte frame length at the tx buffer descriptor is moved to the dma internal tx register. after transmission, the tx status is saved in the tx buffer descriptor. the dma controller then updates the next buffer descriptor pointer for the linked list structure. when the dma tx buffer descriptor register points to the first buffer descriptor, the transmitter starts transmitting the frame data from the buffer memory to tx fifo.
S3C4530A hdlc contr ollers 8- 23 buffer descriptor transmit buffer descriptor 31 15 16 [30:0] buffer data pointer [31] ownership (o) 0 = cpu 1 = dma tx control bits [0] preamble (p) 0 = no preamble 1 = preamble [1] txno crc mode (n) 0 = crc mode 1 = no crc mode [2] little-endian mode (e) 0 = big-endian 1 = little-endian [3] last (l) 0 = this is not the last buffer in the frame. 1 = this is the last buffer inth frame. [4] buffer data pointer decrement (d) 0 = increment 1 = decrement [6:5] widget aligment control (wa) 00 = no invalid bytes 01 =1 invalid bytes 10 = 2 invalid bytes 11 = 3 invalid bytes [23:0] buffer lenght tx status bit this bit may be regarded as valid when the l bit (in tx control bit) is set. [26] transmission completion (t) 0 = normal 1 = one frame completed [31:0] next buffer descriptor pointer the address of the next buffer descriptor 0 18 17 12 13 14 9 10 11 6 7 8 3 4 5 1 2 19 21 20 o 22 23 25 24 26 27 29 28 30 buffer data pointer reserved wa d l e n p reserved t buffer length next buffer descriptor pointer figure 8-10. transmit buffer descriptor
hdlc controllers s3 c4530a 8 - 24 receive buffer descriptor 31 15 16 [30:0] buffer data pointer [31] ownership (o) 0 = cpu 1 = dma [15:0] buffer length received buffer lengths are wrote to this buffer descriptor rx status bits this bits may be regarded as valid when l bit (in rx status bit) is set. [16] cd lost (cd) 0 = normal 1 = cd lost occurs [17] crc error (ce) 0 = normal 1 = crc error occurs to the frame received. [18] non-octet aligned frame (no) 0 = normal 1 = non-octet aligned frame is reveived. [19] over-run (ov) 0 = normal 1 = the reveived frame overruns. [20] dpll two miss (dtm) 0 = normal 1 = dpll two miss clock occurs. [21] rx abort (abt) 0 = normal 1 = the received frame aborted. [22] first in frame (f) 0 = this buffer descriptor status is not the first to the frame. 1 = this buffer descriptor status is the first to the frame. [23] last frame (l) 0 = this buffer descriptor status is not the last to the frame. 1 = this buffer descriptor status is the first to the frame. [24] frame length violation (flv) 0 = normal 1 = this received frame length exceeds the value of the maximum frame length register. [31:0] next buffer descriptor pointer the address of the next buffer descriptor 0 18 17 12 13 14 9 10 11 6 7 8 3 4 5 1 2 19 21 20 o 22 23 25 24 26 27 29 28 30 buffer data pointer reserved reserved f l v buffer length next buffer descriptor pointer l f a b t d t m o v n o c d figure 8-11. receive buffer descriptor
S3C4530A hdlc contr ollers 8- 25 rx buffer descriptor start address pointer buffer data pointer #1 reserved next buffer descriptor status buffer length buffer data pointer #2 reserved next buffer descriptor status buffer length buffer data pointer #n reserved next buffer descriptor status buffer length in single linked lists, the next buffer descriptor is filled with a null address. buffer data #1 unused buffer data #2 unused buffer data #n unused rx bufsize register value rx bufsize register value note: buffer length is accumulated until the last bit is set in status. buffer data pointer indicates the buffer memory start address. figure 8-12. data structure of the receive data buffer
hdlc controllers s3 c4530a 8 - 26 hdlc special registers the hdlc special registers are defined as read-only or write-only registers according to the direction of information flow. the addresses of these registers are shown in table 8-4 and 8-5. the transmitter fifo register can be accessed using two different addresses, the frame terminate address and the frame continue address. the functions of these addresses are discussed in detail in the fifo section below. table 8-4. hdlc channel a special registers registers offset r/w description reset value hmode 0 7000 r/w hdlc mode register 0 00000000 hcon 0 7004 r/w hdlc control register 0 00000000 hstat 0 7008 r/w hdlc status register 0 00000000 hinten 0 700c r/w hdlc interrupt enable register 0 00000000 htxfifoc (frame continue) 0 7010 w htxfifo frame continue register - htxfifot (frame terminate) 0 7014 w htxfifo frame terminate register - hrxfifo 0 7018 r hrxfifo entry register 0 00000000 hbrgtc 0 701c r/w hdlc brg time constant register 0 00000000 hprmb 0 7020 r/w hdlc preamble register 0 00000000 hsar0 0 7024 r/w hdlc station address 0 0 00000000 hsar1 0 7028 r/w hdlc station address 1 0 00000000 hsar2 0 702c r/w hdlc station address 2 0 00000000 hsar3 0 7030 r/w hdlc station address 3 0 00000000 hmask 0 7034 r/w hdlc mask register 0 00000000 hdmatxptr 0 7038 r/w dma tx buffer descriptor pointer 0 ffffffff hdmarxptr 0 703c r/w dma rx buffer descriptor pointer 0 ffffffff hmflr 0 7040 r/w maximum frame length register 0 xxxx0000 hrbsr 0 7044 r/w receive buffer size register 0 xxxx0000 hsync 0x7048 r/w hdlc sync register 0x7e tcon 0x704c r/w transparent control register 0x00000000 tsacfg 0x7800 w tsa configuration register 0x00000000 tsaaslot 0x7804 w tsa a time slot register 0x00000000 tsabslot 0x7808 w tsa b time slot register 0x00000000
S3C4530A hdlc contr ollers 8- 27 table 8-5. hdlc channel b special registers registers offset r/w description reset value hmode 0 8000 r/w hdlc mode register 0 00000000 hcon 0 8004 r/w hdlc control register 0 00000000 hstat 0 8008 r/w hdlc status register 0 00000000 hinten 0 800c r/w hdlc interrupt enable register 0 00000000 htxfifoc (frame continue) 0 8010 w htxfifo frame continue register - htxfifot (frame terminate) 0 8014 w htxfifo frame terminate register - hrxfifo 0 8018 r hrxfifo entry register 0 00000000 hbrgtc 0 801c r/w hdlc brg time constant register 0 00000000 hprmb 0 8020 r/w hdlc preamble register 0 00000000 hsar0 0 8024 r/w hdlc station address 0 0 00000000 hsar1 0 8028 r/w hdlc station address 1 0 00000000 hsar2 0 802c r/w hdlc station address 2 0 00000000 hsar3 0 8030 r/w hdlc station address 3 0 00000000 hmask 0 8034 r/w hdlc mask register 0 00000000 hdmatxptr 0 8038 r/w dma tx buffer descriptor pointer 0 ffffffff hdmarxptr 0 803c r/w dma rx buffer descriptor pointer 0 ffffffff hmflr 0 8040 r/w maximum frame length register 0 xxxx0000 hrbsr 0 8044 r/w receive buffer size register 0 xxxx0000 hsync 0x8048 r/w hdlc sync register 0x7e tcon 0x804c r/w transparent control register 0x00000000
hdlc controllers s3 c4530a 8 - 28 hdlc global mode register table 8-6. hmodea and hmodeb register registers offset r/w description reset value hmodea 0 7000 r/w hdlc mode register 0 00000000 hmodeb 0 8000 r/w hdlc mode register 0 00000000 table 8-7. hmode register description bit number bit name description [0] multi-frame in htxfifo in dma operation (mff) if this bit is set, more than one frame can be loaded into htxfifo. in this case, the frame size may be less than the fifo size. [1] reserved not applicable. [2] rx clock inversion(rxcinv) if this bit is set to '0', the receive clock samples the data at the rising edge. if this bit is set to '1', the receive clock samples the data at the falling edge. [3] tx clock inversion(txcinv) if this bit is set to '0', the transmit clock shifts the data at the falling edge. if this bit is set to '1', the transmit clock shifts the data at the rising edge. [4] rx little-endian mode (rxlittle) this bit determines whether the data is in little- or big-endian format. hrxfifo is in little-endian. if this bit is set to '0', then the data on the system bus should be in big-endian. therefore the bytes will be swapped in big- endian. [5] tx little-endian mode (txlittle) this bit determines whether tx data is in little or big endian (txlittle) format. htxfifo is in little-endian. if this bit is set to '1', the data on the system bus is little endian. if this bit is set to '0', the data on the system bus is in big-endian. (that is, the data bytes are swapped to be little endian format.) [6] rx transparent mode (rxtrans) if this bit set to one, hdlc rx operates transparent mode. otherwise, operates hdlc mode. [7] tx transparent mode (txtrans) if this bit set to one, hdlc tx operates transparent mode. otherwise, operates hdlc mode. [10:8] tx preamble length(txpl) these bits determine the length of preamble to be sent before the opening flag when the txprmb bit is set in the control register. 000 1byte, 001 2bytes, ..., and 111 8bytes will be sent. [11] reserved not applicable. [14:12] data formats (df) when the df bits are '000', data is transmitted and received in the nrz data format. when df is '001', the nrzi (zero complement) data format is selected. df = '010' selects the fm0 data format, df = '011' the fm1 data format, and df = '100' the manchester data format. [15] reserved not applicable. [18:16] dpll clock select (dpllclk) using this setting, you can configure the clock source for dpll to one of the following pins: txc, rxc, mclk, brgout1, or brgout2. to select one of these pins, set the dpllclk bits to '000', '001', '010', '011', or '100', respectively.
S3C4530A hdlc contr ollers 8- 29 table 8-7. hmode register description (continued) bit number bit name description [19] brg clock select (brgclk) if this bit is '1', mclk2 is selected as the source clock for the baud rate generator (brg). if this bit is '0', the external clock at the rxc pin is selected as the brg source clock. [22:20] tx clock select (txclk) using this setting, you can configure the transmit clock source to one of the following pins: txc, rxc, dplloutt, brgout1, or brgout2. to select one of these pins, set the txclk bits to '000', '001', '010', '011', or '100', respectively. [26:24] rx clock select (rxclk) using this setting, you can configure the receive clock source to one of the following pins: txc, rxc, dplloutr, brgout1, or brgout2. to select one of these pins, set the rxclk bits to '000', '001', '010', '011', or '100', respectively. [30:28] txc output pin select (txcops) if you do not use the clock at the txc pin as the input clock, you can use the txc pin to monitor txclk, rxclk, brgout1, brgout2, dplloutt, and dplloutr. to select the clock you want to monitory, set the txcops to '000', '001', '010', '011', or '100', respectively. [31] reserved not applicable.
hdlc controllers s3 c4530a 8 - 30 [0] muilt-frame in txfifo in dma opeatiom (mff) 0 = single frame in txfifo 1 = multi frame in txfifo [1] reserved [2] rx clock inversion (rxcinv) 0 = rx clock rising 1 = rx clock falling [3] tx clock inversion (txcinv) 0 = tx clock falling 1 = tx clock rising [4] rx little-endian mode (rxlittle) 0 = the rx data on the system bus is in big-endian format. 1 = the rx data on the system bus is in little-endian format. [5] tx little-endian mode (txlittle) 0 = the tx data on the system bus is in big-endian format. 1 = the tx data on the system bus is in little-endian format. [6] rx transparent mode (rxtrans) 0 = normal hdlc 1 = transparent operation [7] tx transparent mode (txtrans) 0 = normal hdlc 1 = transparent operation [10:8] tx preamble length (txpl) 000 = 1 byte 010 = 3 byte 100 = 5 byte 110 = 7 byte 001 = 2 byte 011 = 4 byte 101 = 6 byte 111 = 8 byte [11] reserved [14:12] data format (df) 000 = nrz 001 = nrzi 010 = fm0 011 = fmi 100 = machester [15] reserved [18:16] dpll clock select (dpllclk) 000 = txc pin 001 = rxc pin 010 = mclk 011 = brgout1 100 = brgout2 [19] brg clock select (brgclk) 0 = rxc pin is selected. 1 = mclk2 is selected. [22:20] tx clock select (txclk) 000 = txc pin 001 = rxc pin 010 = dplloutt 011 = brgout1 100 = brgout2 [23] reserved [26:24] rx clock select (rxclk) 000 = txc pin 001 = rxc pin 010 = dplloutt 011 = brgout1 100 = brgout2 [27] reserved [30:28] txc output pin select (txcops) this pin is used for output only when it is not used as an input clock for th dpll, txclk, or rxclk. 000 = tx clock 001 = rx clock 010 = brgout1 011 = brgout2 100 = dplloutt 101 = dplloutr [31] reserved 31 0 3 4 5 1 2 txc ops 30 29 28 27 26 25 23 22 20 19 15 14 10 9 24 21 18 17 16 13 12 11 8 7 6 rxclk txclk b r g c l k dpll clk df t x l i t t l e txpl r x l i t t l e t x c i n v r x c i n v m f f t x t r a n s r x t r a n s figure 8-13. hmode register
S3C4530A hdlc contr ollers 8- 31 hdlc control register table 8-8. hcona and hconb register registers offset r/w description reset value hcona 0 7004 r/w hdlc channel a control register 0x00000000 hconb 0x8004 r/w hdlc channel b control register 0x00000000 table 8-9. hcon register description bit number bit name description [0] tx reset (txrs) set this bit to '1' to reset the tx block. tx block comprises htxfifo and a transmitter block. [1] rx reset (rxrs) set this bit to '1' to reset the rx block. rx block comprises hrxfifo and a receiver block. [2] dma tx reset (dtxrs) set this bit to '1' to reset the dma tx block. [3] dma rx reset (drxrs) set this bit to '1' to reset the dma rx block. [4] tx enable (txen) when the txen bit is '0', the transmitter enters a disabled state and the line becomes high state. in this case, the transmitter block is cleared except for the htxfifo and the status bits associated with transmit operation are cleared. data cannot be loaded into the htxfifo. if this bit is set to '1', the idle pattern is sent continuously. in this case, the data can be loaded into htxfifo, and then sent. [5] rx enable (rxen) when the rxen bit is '0', the receiver enters a disabled state and can not detect the flag pattern, if any. in this case, receiver block is cleared except for the hrxfifo and the status bits associated with receiver operation are cleared. data cannot be received. if this bit is set to '1', the flag pattern is detected. in this case, the data received can be loaded into the hrxfifo, and moved to system memory. [6] dma tx enable (dtxen) the dtxen bit lets the hdlc tx operate on a bus system in dma mode. when dma tx is enabled, an interrupt request caused by txfa status is inhibited and the hdlc does not use the interrupt request to request a data transfer. dma tx monitors the htxfifo and fills the htxfifo. this bit is auto disabled when tx under-run occurs, or cts lost, or next buffer descriptor pointer reach null, or the owner bit is not dma mode when dtxstsk bit is set. if tx under-run occurs, dtxabt(in hstat) bit set, and abort signal sent. if cts lost occurs, dtxabt bit set and txd output goes high state as long as cts remains high level.
hdlc controllers s3 c4530a 8 - 32 table 8-9. hcon register description (continued) bit number bit name description [7] dma rx enable (drxen) the drxen bit lets the hdlc rx operate on a bus system in dma mode. when dma rx is enabled, an interrupt request caused by the rxfa status is inhibited, and the hdlc does not use the interrupt request to request a data transfer. dma rx monitors the hrxfifo and moves the data from the hrxfifo to memory. this bit is automatically disabled when the next buffer descriptor pointer becomes null, or the owner bit is not in dma mode when the dtxstsk bit is set. [8] dpll enable (dpllen) setting this bit enables the dpll, causing the dpll to enter search mode. in search mode, the dpll searches for a locking edge in the incoming data stream. after dpll is enabled (in nrzi mode for example), the dpll starts sampling immediately after the first edge is detected. (in fm mode, the dpll examines the clock edge of every other bit to decide what correction must be made to remain in sync.) if the dpll does not detect an edge during the expected window, it sets the one clock missing bit. if the dpll does not detect an edge after two successive attempts, it sets the two clock missing bit and the dpll automatically enters the search mode. to reset both clocks missing latches, you can disable and re-enable the dpll using the reset rx status. [9] brg enable (brgen) this bit controls the operation of the baud rate generator (brg). to enable the brg counter, set the brgen bit to '1'. to inhibit counting, clear the bit to '0'. [10] tx 4 word mode (tx4wd) when this bit is '0', and txfa bit in status register is '1', it is indicated that tx fifo is empty for 1 word. it means that 1-word data can be loaded to tx fifo. similarly, when this bit is '1', the same status register bit indicate that 4 words of data can be loaded to tx fifo without reading the status bit for a second time. specifically, the status register bit affected by the 1-word or 4-word transfer setting are the transmit data available (txfa) bit. [11] rx 4 word mode (rx4wd) when this bit is '0', and the rxfa bit in the status register is '1', it is indicated that rx fifo has 1-word data. it means that 1 word data can be moved to memory. similarly, when this bit is '1', the same status register bit indicates that 4 words of data can be moved in the memory without reading the status bit for a second time. specifically, the status register bit affected by the 1-word or 4-word transfer setting are the receive data available (rxfa) bit, and the residue bytes status bits, rxrb[3:0].
S3C4530A hdlc contr ollers 8- 33 table 8-9. hcon register description (continued) bit number bit name description [13:12] rx widget alignment (rxwa) these bits determine how many bytes are invalid in the first memory word of the frame to be received. the invalid bytes are inserted when the word is assembled in the hrxfifo. '00' =no invalid bytes; '01' = 1 invalid byte, '10' = 2 invalid bytes, '11' = 3 invalid bytes. [14] dma tx stop or skip (dtxstsk) this bit determines a dma tx stop or skip when dma has not the ownership associated with the tx buffer descriptor. dma tx is disabled in this condition when this bit is set. [15] dma rx stop or skip (drxstsk) this bit determines a dma rx stop or skip when dma has not the ownership associated with the rx buffer descriptor. if this bit is set, dma rx is disabled. [16] dma rx memory address decrement (drxmadec) this bit determines whether the address is increased or decreased. if this bit is set to '1', then the address will be decremented. [17] tx flag idle (txflag) this bit selects the flag 'time fill' mode (active idle) or the mark idle mode (inactive idle) for the transmitter. the selected active or inactive idle state continues until data is sent (after nreset has return to high level). the flag idle pattern is 7eh; the mark idle pattern is ffh. [18] tx single flag (txsflag) this bit controls whether separate closing and opening flags are transmitted in succession to delimit frames. when this bit is '0', independent opening and closing flags are transmitted in order to separate frame. when this bit is set to '1', the closing flag of the current frame serves as the opening flag of the next frame. [19] tx loop-back mode (txloop) this bit is used for self-testing. if this bit is set to '1', the transmit data output (txd) is internally connected to the receiver data input (rxd). in loop-back mode, ncts and ndcd inputs are ignored. for normal operation, this bit should always be '0'. [20] rx echo mode (rxecho) setting this bit to '1' selects the auto-echo mode of operation. in this mode, the txd pin is connected to rxd as in local loop-back mode, but the receiver still monitors the rxd input. [21] tx abort extension (txabtext) when this bit is set to '1', the abort pattern that is initiated when txabt = '1' is extended to at least 16 bits of 1s in succession, and the mark idle state is entered. [22] tx abort (txabt) when this bit is set to '1', an abort sequence of at least eight bits of 1s is transmitted. the abort is initiated and the htxfifo is cleared. txabt is then cleared automatically by hardware.
hdlc controllers s3 c4530a 8 - 34 table 8-9. hcon register description (continued) bit number bit name description [23] tx preamble (txprmb) when this bit is set to '1', the content of the hprmb register is transmitted as many txpl bit values in interrupt mode instead of mark idle or time fill mode. this is useful for sending the data needed by the dpll to lock the phase. in dma mode, this bit is meaningless. [24] tx data terminal ready (txdtr) the txdtr bit directly controls the ndtr output state. setting this bit forces the ndtr pin to low level. when you clear the txdtr bit, ndtr goes high. [25] rx frame discontinue (rxdiscon) when this bit is set, the frame currently received is ignored and the data in this frame is discarded. only the last frame received is affected. there is no effect on subsequent frames, even if the next frame enters the receiver when the discontinue bit is set. this bit is automatically cleared after a cycle. [26] tx no crc (txnocrc) when this bit is set to '1', the crc is not appended to the end of a frame by hardware. [27] rx no crc (rxnocrc) when this bit is set to '1', the receiver does not check for crc by hardware. (crc data is always moved to the hrxfifo.) [28] auto enable (autoen) this bit programs the function of both ndcd and ncts. however, txen and rxen must be set before the ncts and ndcd pins can be used. when this bit is '0', if the ncts becomes high, the transmitter sends mark idle pattern. however, though the ndcd becomes high, the receiver can receive the data. when this bit is '1', if the ncts becomes high, the transmitter send mark idle but clears the htxfifo and the tx block. if ndcd becomes high, the receiver can't operate, and the hrxfifo and rx blocks are cleared. [29] transparent rx stop (trxstop) this bit reset value is zero. if this bit set to one, the receive operation is ended in transparent mode. and then the receiver start to search sync. if this bit set to one in hdlc mode, rx fifo cleared except for receiver. so, the data in receiver can be moved to rx fifo at this time. [30] transmit reverse (txrev) if this bit set to one, the data will be sent msb first. if this bit set to zero, lsb first. [31] receive reverse (rxrev) if this bit set to one, the received data will be msb first. if this bit set to zero, lsb first.
S3C4530A hdlc contr ollers 8- 35 [0] tx reset (txrs) 0 = normal 1 = txfifomand tx block are reset. [1] rx reset (rxrs) 0 = normal operation 1 = rxfifo and tx block are reset. [2] dma tx reset (dtxrs) 0 = normal operation 1 = dma tx block is reset. [3] dma rx reset (drxrs) 0 = normal operation 1 = dma rx block is reset. [4] tx enable (txen) 0 = tx disabled 1 = tx enabled [5] rx enable (rxen) 0 = rx disabled 1 = rx enabled [6] dma tx enable (dtxen) 0 = dma tx disabled 1 = dma tx enabled [7] dma rx enable (drxen) 0 = dma rx disabled 1 = dma rx enabled [8] dpll enable (dpllen) 0 = disable 1 = enable; dpll enters search mode for a locking edge in the incoming data stream. [9] brg enable (brgen) 0 = brg counter is inbibited. 1 = brg counter is enabled. [10] tx 4 word burst mode (tx4wd) 0 = 1-word mode selected. 1 = 4-word mode selected. [11] rx 4 word burst mode (rx4wd) 0 = 1-word mode selected. 1 = 4-word mode selected. [13:12] rx widget algnment (rxwa) 00 = no invalid byte 01 = 1 invalid byte 10 = 2 invalid byte 11 = 3 invalid byte [14] dma tx stop or skip (dtxstsk) 0 = dma tx skips when dma not owner bit is set. 1 = dma tx stops when dma not owner bit is set. [15] dma rx stop or skip (drxstsk) 0 = dma rx skips when dma not owner bit is set. 1 = dma rx stops when dma not owner bit is set. [16] dma rx stop or skip (drxmadec) 0 = address is incremented. 1 = address is decremented. [17] tx flag idle (txflag) 0 = enter mark idle mode (a bit pattern of consecutive ones) 1 = enter time fill mode (a bit pattern of consecutive opening (closing) flag, as in string 01111110 01111110...... 31 0 3 4 5 1 2 30 29 28 27 26 25 23 22 20 19 15 14 10 9 24 21 18 17 16 13 12 11 8 7 6 a u t o e n r x e n t x e n r x d i s c o n r x n o c r c t x n o c r c t x d t r t x p r m b t x a b t t x a b t e x t r x e c h o t x l o o p t x s f l a g t x f l a g d r x m a d e c d r x s t s k d t x s t s k r x 4 w d t x 4 w d b r g e n d p l l e n d r x e n d t x e n r x w a d t x r s r x r s d r x r s t x r s r x r e v t x r e v t r x s t o p figure 8-14. hdlc control register (hcon)
hdlc controllers s3 c4530a 8 - 36 [18] tx single flat (txsflag) 0 = double flag mode (a closing & opening flags are used to separate frames) 1 = single flag mode (only one flags are used to separate frames) [19] tx loop-back mode (txloop) 0 = normal operation. 1= the tramsmit data output is internally connected to the receiver data input for self testing . [20] rx echo mode (rxecho) 0 = disable tx auto-echo mode. 1 = enable rx dma tx block is reset. [21] tx abort extension (txabtext) 0 = at least consecutive eigth 1s are transferred. 1 = at least 16 consecutive 1s are transferred. [22] tx abort (txabt) 0 = normal 1 = enable (at least eight consecutive 1s are trnasmitted.) [23] tx preamble (txprmb) 0 = transmit a mark idle is time fill bit pattern. 1 = transmit the content of hprmb [24] tx data terminology ready (txdtr) 0 = ndtr goes high level. 1 = ndtr goes low level. [25] rx frame discontinue (txdiscon) 0 = normal 1 = ignore the currently received frame [26] tx no crc (txnocrc) 0 = disable 1 = crc is not appended by hardware. [27] rx no crc (rxnocr) 0 = disable 1 = receiver does not check crc by hardware. (crc is treated as data in any case) [28] auto enable (autoen) 0 = normal operation. even if the ncts or ndcd become high, the transmitter can send tx data and the receiver can receive rx data. 1 = if the ndcd or ncts become high, the transmitter can not send tx data and the receiver can not receive rx data. [29] transparent rx stop (trxstop) 0 = normal 1 = stop receive operation. [30] tx reverse (txrev) 0 = normal 1 = send tx data reversly. [29] rx reverse (rxrev) 0 = normal operation 1 = receive rx data reversly. 31 0 3 4 5 1 2 30 29 28 27 26 25 23 22 20 19 15 14 10 9 24 21 18 17 16 13 12 11 8 7 6 a u t o e n r x e n t x e n r x d i s c o n r x n o c r c t x n o c r c t x d t r t x p r m b t x a b t t x a b t e x t r x e c h o t x l o o p t x s f l a g t x f l a g d r x m a d e c d r x s t s k d t x s t s k r x 4 w d t x 4 w d b r g e n d p l l e n d r x e n d t x e n r x w a d t x r s r x r s d r x r s t x r s r x r e v t x r e v t r x s t o p figure 8-14. hdlc control register (hcon) (continued)
S3C4530A hdlc contr ollers 8- 37 hdlc status register (hstat) note reading the hdlc status register is a non-destructive process. the method used to clear a high-level status condition depends on the bit's function and operation mode(dma or interrupt). for details, please see the description of each status register. table 8-10. hstata and hstatb register registers offset r/w description reset value hstata 0x7008 r/w hdlc channel a status register 0x00000000 hstatb 0x8008 r/w hdlc channel b status register 0x00000000 summary there are two kinds of bits in a status register. 1. txfa, txcts, rxfa, rxdcd, rxfv, rxcrce, rxno, rxierr, and rxov bits are show each bit's status. these bits are set or cleared automatically according to the status of each bit. 2. all other bits are cleared by the cpu writing '1' to each bit.
hdlc controllers s3 c4530a 8 - 38 table 8-11. hstat register description bit number bit name description [3:0] rx remaining bytes (rxrb) (rxrb + 1) indicates how many data bytes are valid in a 1-word or 4-word boundary when the receiver has received a complete frame. in 1-word transfer mode, the rxrb value is either 0, 1, 2, or 3. in 4-word mode, it is 0, 1, ..., 14, or 15. [4] tx frame complete (txfc) this status bit is automatically set to '1' when the two conditions are met: 1) there is no data in the tx fifo, and 2) either an abort or a closing flag is transmitted. you can clear this bit by writing '1' to this bit. [5] tx fifo available (txfa) if this bit is '1', the data to be sent can be loaded into the htxfifo register. in 1-word transfer mode, the txfa status bit is set to '1' when the first register of the htxfifo is empty. in 4-word transfer mode, txfa = '1' when the first four 32-bit registers of the htxfifo are empty. the txfa status condition is automatically cleared when htxfifo is no longer available. during dma tx operation, this bit is always '0', so not generating interrupt. [6] tx clear-to-send (txcts) the ncts input is projected to this status bit. if the level at the ncts input pin is low, this status bit is'1'. if ncts input pin is high level, txcts is '0'. this bit does not generate an interrupt. [7] tx stored clear-to-send (txscts) this bit is set to '1' each time a transition in ncts input occurs. you can clear this bit by writing '1' to this bit. [8] tx under-run (txu) when the transmitter runs out of data during a frame transmission, an under-run occurs and the frame is automatically terminated by transmitting an abort sequence. the under-run condition is indicated when txu is '1'. you can clear this bit by writing a '1' to this bit. [9] rx fifo available (rxfa) this status bit indicates when the data received can be read from the rx fifo. when rxfa is '1', it indicates that data (other than an address or a final data word) is available in the hrxfifo. in 1-word transfer mode, rxfa bit set to '1' when received data is available in the last fifo register. in 4-word transfer mode, it is set to '1' when the data received is available in the last four 32-bit fifo registers. even if the data reside in fifo for only two words, when the last bit is set, rx fifo is regarded as valid. (the received data available condition is cleared automatically when the data received is no longer available.) during dma rx operation, this bit is always zero, so does not generate an interrupt. [10] tx frame good (txfg) this bit set to one when one frame sent well.
S3C4530A hdlc contr ollers 8- 39 table 8-11. hstat register description (continued) bit number bit name description [11] rx flag detected (rxfd) this bit is set to one when the last bit of the flag sequence is received. this bit generates an interrupt if enabled. you can clear this bit by writing one to this bit. [12] rx data carrier detected (rxdcd) the dcd status bit mirrors the state of the ndcd input pin. if ndcd input pin is low, this status bit is '1'. if ndcd input pin is high, it is '0'. this bit does not generate an interrupt. [13] rx stored data carrier detected (rxsdcd) this bit is set to '1' when a transition in ndcd input occurs, and can generate interrupt, if enabled. you can clear this bit by writing a '1' to this bit. [14] rx frame valid (rxfv) this bit signals frame's ending boundary to the cpu and also indicates that no frame error occurred. it is set when the last data byte of a frame is transferred into the last location of the rx fifo and is available to be read. [15] rx idle (rxidle) the rxidle status bit indicates that a minimum of 15 consecutive 1s have been received. the event is stored in the status register and can be used to trigger a receiver interrupt. the rxidle bit continues to reflect the inactive idle condition until a '0' is received. you can clear this bit by writing a '1' to this bit. [16] rx abort (rxabt) the rxabt status bit is set to '1' when seven or more consecutive 1s (abort sequence) have been received. when an abort is received in an 'in- frame' condition, the event is stored in the status register triggering an interrupt request. you can clear this bit by writing a '1' to this bit. [17] rx crc error (rxcrce) the rxcrce status bit is set a frame is completed with a crc error. [18] rx non-octet align (rxno) the rxno bit is set to '1', if received data is non-octet aligned frame. [19] rx overrun (rxov) the rxov status bit is set to '1', if the data received is transferred into the hrxfifo when it is full, resulting in a loss of data. continued overruns destroy data in the first fifo register. [20] dma rx memory overflow (rxmov) this bit is set when there is no more buffer during receiving data. if this bit is set, drxen bit is cleared. you can clear this bit by writing '1' to this bit. [21] reserved. not applicable. [22] dma tx abort (dtxabt) this bit is set to one when abort signal is sent due to the tx under-run or cts lost occurred. if this bit is set, dtxen(in hcon) bit cleared. you can clear this bit by writing '1' to this bit.
hdlc controllers s3 c4530a 8 - 40 table 8-11. hstat register description (continued) bit number bit name description [23] rx internal error (rxierr) this bit is set to '1' when received frame will be detected error possibility due to the receive clock is unstable. [24] dma rx frame done every received frame (drxfd) this bit is set when a dma rx operation has successfully operated a frame to memory from hrxfifo, and when the last byte of a frame has been written to memory. this bit generate interrupt when set to '1' to know a frame is received. you can clear this bit by writing '1' to this bit. [25] dma rx null list (drxnl) if this bit is set, the dma rx buffer descriptor pointer has a null address. in this case, dma rx is disabled and the data transfer from the rx fifo to buffer memory is discontinued. so the hrxfifo is cleared. you can clear this bit by writing '1' to this bit. [26] dma rx not owner (drxno) this bit is set, when dma is not owner of the current buffer descriptor, and drxstsk bit was set. in this case, dma rx is disabled and can generate interrupt, if enabled. if drxstsk bit is zero, this bit is always zero. you can clear this bit by writing '1' to this bit. [27] dma tx frame done (dtxfd) this bit is set to '1' when dma tx operation has successfully transferred a frame from memory to tx fifo. you can clear this bit by writing '1' to this bit. [28] dma tx null list (dtxnl) if this bit is set '1', the dma tx buffer descriptor pointer has a null address. in this case, dma tx is disabled and the data to be transferred discontinued from the buffer memory to tx fifo. you can clear this bit by writing '1' to this bit. [29] dma tx not owner (dtxno) this bit is set, when dma is not owner of the current buffer descriptor, and dtxstsk bit was set. in this case, dma tx disabled and can generate interrupt, if enabled. if dtxstsk bit is zero, this bit is always zero. you can clear this bit by writing '1' to this bit. [30] dpll one clock missing (dpllom) when operating in fm/manchester mode, the dpll sets this bit to '1' if it does not detect an edge in its first attempt. you can clear this bit by writing a '1' to this bit. [31] dpll two clock missing (dplltm) when it is operating in the fm/manchester mode, the dpll sets this bit to '1' if it does not detect an edge in two successive attempts. at the same time the dpll enters search mode. in nrz/nrzi mode, and while the dpll is disabled, this bit is always '0'. you can clear this bit by writing a '1' to this bit.
S3C4530A hdlc contr ollers 8- 41 [3:0] rx remaining bytes (rxrb) at 1-word boundary: at 4-word boundary: 0000 = valid data byte is 1 0000 = valid data byte is 1 0001 = valid data byte is 2 . 0010 = valid data byte is 3 . 0011 = valid data byte is 4 1111 = valid data byte is 16 [4] tx frame complete (txfc) 0 = normal operation 1 = automatically set; if two conditions are met: 1) tx fifo is empty. 2) an abort or a closing flag is transmitted. [5] tx fifo available (txfa) 0 = tx fifo is not available. 1 = tx fifo is available. (that is, the data to be transmitted can now be loaded into the tx fifo.) [6] tx clear-to send (txcts) 0 = level at the ncts input pin is high. 1 = level at the ncts input pin is low. [7] tx stored clear-to-send (txscts) 0 = normal operation 1 = a transition occured at the ncts input. (this transition can be used to trigger an interrupt.) [8] tx underrun (txu) 0 = normal operation 1 = the transmitter ran out of data during transmission. [9] rx fifo available (rxfa) 0 = normal operation 1 = data is available in the rxfifo. [10] tx frame good (txfg) 0 = normal operation 1 = tx data sent well. [11] rx flag detected (rxfd) 0 = normal operation 1 = this bit is set, when the last bit of the flag sequence is received. [12] rx data-carrier-detected (rxdcd) 0 = ndcd input pin is high 1 = ndcd input pin is low [13] rx stored data-carrier-detected (rxsdcd) 0 = normal operation 1 = when a transition of the ndcd input occurs, this bit is set. [14] rx frame valid (rxfv) 0 = normal operation 1 = the last data byte if a frame is transgerred into the last location of rxfifo. [15] rx idle (rxidle) 0 = normal operation 1 = a minimum 15 consecutive 1s have been reveived. 31 0 3 4 5 1 2 30 29 28 27 26 25 23 22 20 19 15 14 10 9 24 21 18 17 16 13 12 11 8 7 6 d t x n l t x f a t x f c d r x n l d t x f d d r x n o d r x f d r x i e r r d t x a b t r x m o v r x o v r x n o r x c r c e r x a b t r x i d l e r x f v r x f d r x f a t x u t x s c t s t x c t s r x s d c d r x r b d p l l t m d p l l o m d t x n o r x d c d t x f g figure 8-15. hdlc status register
hdlc controllers s3 c4530a 8 - 42 [16] rx abort (rxabt) 0= normal operation 1 = seven or more consecutive 1s have been received, in-frame condition. [17] rx crc error (rxcrce) 0 = normal operation 1 = a frame rx operation is completed with a crc error. [18] rx non-octet align (rxno) 0 = received frame is octet. 1 = received frame is not octet. [19] rx overrun (rxov) 0 = normal operation 1 = received data is transferred into the rxfifo when it is full. [20] rx memory overflow (rxmov) 0 = normal operation 1 = indicates memory overflow when rx buffer descriptor next pointer has null address. [21] reserved [22] dma tx abort (dtxabt) 0 = normal operation 1 = abort signal is sended and dma tx enable bit is cleared. [23] rx internal error (rxierr) 0 = normal operation 1 = received frame is not stable due to receive clock is unstable. [24] dma rx frame done every received frame (drxfd) 0 = normal operation 1 = dma rx operation has successfully transferred a frame from rxfifo to buffer memory. [25] dma rx null list (drxnl) 0 = normal operation 1 = dma rx buffer descriptor pointer has a null address. [26] dma rx not owner (drxno) 0 = dma has the ownership. 1 = cpu has the ownership. [27] dma tx frame done (dtxfd) 0 = normal operation 1 = dma tx operation has successfully transferred a frame from memory to txfifo. [28] dma tx null list (dtxnl) 0 = normal operation 1 = dma tx buffer descriptor pointer has a null address. [29] dma tx not owner (dtxno) 0 = dma has the ownership. 1 = cpu has the ownership. [30] dpll one clock missing (dpllom) 0 = normal operation 1 = set in fm/machester mode when dpll does not detect an edge on the first entry. [31] dpll two clock missing (dplltm) 0 = normal operation 1 = dpll was not detected on two consecutive edges an search mode sas entered. 31 0 3 4 5 1 2 30 29 28 27 26 25 23 22 20 19 15 14 10 9 24 21 18 17 16 13 12 11 8 7 6 d t x n l t x f a t x f c d r x n l d t x f d d r x n o d r x f d r x i e r r d t x a b t r x m o v r x o v r x n o r x c r c e r x a b t r x i d l e r x f v r x f d r x f a t x u t x s c t s t x c t s r x s d c d r x r b d p l l t m d p l l o m d t x n o r x d c d t x f g figure 8-15. hdlc status register (continued)
S3C4530A hdlc contr ollers 8- 43 hdlc interrupt enable register (hinten) table 8-12. hintena and hintenb register registers offset r/w description reset value hintena 0x700c r/w hdlc interrupt enable register 0x00000000 hintenb 0x800c r/w hdlc interrupt enable register 0x00000000 table 8-13. hinten register description bit number bit name description [3:0] reserved ? [4] txfcie tx frame complete interrupt enable [5] txfaie tx fifo available to write interrupt enable [6] reserved [7] txsctsie cts transition has occurred interrupt enable [8] txuie tx under-run has occurred interrupt enable [9] rxfaie rx fifo available to read interrupt enable [10] txfgie tx frame good interrupt enable [11] rxfdie rx flag detected interrupt enable [12] reserved [13] rxsdcdie dcd transition interrupt enable [14] rxfvie rx frame valid interrupt enable [15] rxidleie idle detected interrupt enable [16] rxabtie abort detected interrupt enable [17] rxcrceie crc error frame interrupt enable [18] rxnoie non-octet aligned frame interrupt enable [19] rxovie rx overrun interrupt enable [20] rxmovie rx memory overflow interrupt enable [21] reserved [22] dtxabtie dma tx abort interrupt enable [23] rxierrie rx internal error interrupt enable [24] drxfdie dma rx frame done interrupt enable [25] drxnlie dma rx null list interrupt enable [26] drxnoie dma rx not owner interrupt enable [27] dtxfdie dma tx frame done every transmitted frame interrupt enable [28] dtxnlie dma tx null list interrupt enable [29] dtxnoie dma tx not owner interrupt enable [30] dpllomie dpll one clock missing interrupt enable [31] dplltmie dpll two clocks missing interrupt enable
hdlc controllers s3 c4530a 8 - 44 [3:0] reserved [4] tx frame complete interrupt enable (txfcie) [5] tx fifo available to write interrupt enable (txfaie) [6] reserved [7] cts transition has occurred interrupt enable (txsctie) [8] transmit underrun has occured interrupt enable (txuie) [9] rxfifo available to read interrupt enable (rxfaie) [10] tx frame good interrupt enable (txfgie) [11] flag detected interrupt enable (rxfdie) [12] reserved [13] dcd transition interrupt enable (rxsdcdie) [14] valid frame interruopt enable (rxfvie) [15] idle detected interruot enable (rxidleie) [16] abort detected interrupt enable (rxabtie) [17] crc error frame interrupt enable (rxcrceie) [18] non-dctet aligned frame interrupt enable (rxnoie) [19] rx overrun interrupt enable (rxovie) [20] rx memory overflow interrupt enable (rxmovie) [21] reserved [22] dma tx abort interrupt enable (dtxabtie) [23] rx internal error interrupt enable (rxierrien) [24] dma rx frame done every received frame interrupt enable (drxfdie) [25] dma rx null list interrupt enable (drxnlie) [26] dma rx not owner interrupt enable (drxnoie) [27] dma tx frame done every received frame interrupt enable (dtxfdie) [28] dma tx null list interrupt enable (dtxnlie) [29] dma tx not owner interrupt enable (dtxnoie) [30] dpll one missing interrupt enable (dpllomie) [31] dpll two missing interrupt enable (dplltmie) 31 0 3 4 5 1 2 30 29 28 27 26 25 23 22 20 19 15 14 10 9 24 21 18 17 16 13 12 11 8 7 6 d t x n l i e t x f a i e t x f c i e d r x n l i e d t x f d i e d r x n o i e d r x f d i e r x i e r r i e d t x a b t i e r x m o v i e r x o v i e r x n o i e r x c r c e i e r x a b t i e r x i d l e i e r x f v i e r x f d i e r x f a i e t x u i e t x s c t s i e r x s d c d i e d p l l t m i e d p l l o m i e d t x n o i e t x f g i e figure 8-16. hdlc interrupt enable register
S3C4530A hdlc contr ollers 8- 45 hdlc tx fifo (htxfifo) the tx fifo consists of eight 32-bit registers that are used for buffer storage of data to be transmitted. data is always transferred from a full register to an empty adjacent register. the tx fifo can be addressed at two different register addresses: the 'frame continue' address and the 'frame terminate' address. each register has four pointers, data valid pointer bit (4 bits), last pointer bit, nocrc pointer bit, preamble pointer bit. the data valid pointer bit indicates whether each byte is valid or not. the last byte pointer bit indicates whether the frame to be sent has the frame last byte or not. the nocrc pointer bit determines whether the crc data is to be appended or not by hardware. when a valid data byte is written to the 'frame continue' address, the data valid pointer is set, but the last byte pointer is not set. when a valid data byte is written to the 'frame terminate' address, the data valid pointer and last byte pointer are set together. to reset these pointers, you write a '1' to either the txabt bit or the txrs bit in the hcon register. in dma mode, when the dma controller writes data to the htxfifo, tx buffer descriptor buffer length field value must be pre-set. however, if the last bit is set in buffer descriptor, the last byte pointer in htxfifo is also set. this means the last byte of the frame is in htxfifo. if the transmitted frame is longer than the buffer length field value, the last byte pointer will not be set, and the next buffer descriptor having the last byte pointer bit will be used. the pointers continue shifting through the fifo. when the transmitter detects a positive transition in the data valid pointer at the last location of the fifo, it initiates a frame with an opening flag. when it detects a negative transition in the last byte pointer at the last location of the fifo, it closes the frame, appending the crc and a closing flag follows. the status of the tx fifo is indicated by the transmitter fifo register available (txfa) status bit. when txfa = '1', the tx fifo is available for loading data and data can be loaded into it. (this function is controlled by the tx4wd bit.) the htxfifo is reset by writing a '1' to the tx reset, or the txabt bit or by the nreset. during a reset operation, the txfa status bit is suppressed and data loading is inhibited. 8 tx data txfifo data valid (4-bit) 8-bit 8-bit 8-bit 8-bit last (1-bit) nocrc preamble figure 8-17. hdlc tx fifo function diagram
hdlc controllers s3 c4530a 8 - 46 hdlc rx fifo (hrxfifo) the rx fifo consists of eight 32-bit registers that are used for the buffer storage of the data received. data bytes are always transferred from a full register to an adjacent empty register. each register has pointer bits that indicate the frame status. when these pointers appear at the last 1-word or 4-word fifo location, they update the last bit(indicating the last of a frame), the overrun bit, the crc error bit, or non-octet aligned bit. the hrxfifo data available (rxfa) status bits indicate the current state of the hrxfifo. when the hrxfifo data status bit is '1', the hrxfifo is ready to be read. the hrxfifo data status is controlled by the 4-word or 1- word transfer selection bit (rx4wd). when an overrun occurs, the overrun frame of the hrxfifo is no longer valid. an 'in frame' abort or a high level on ndcd input with the autoen bit in hcon is set to '1', the frame is cleared in the hrxfifo. (the last byte of the previous frame, which is separated by the frame boundary pointer, is retained). data in hrxfifo should be read by word size. the hrxfifo is cleared by the rx reset bit set to '1', an abort signal received, or nreset rx data rxfifo data valid 8-bit 8-bit 8-bit 8-bit last ov crce no figure 8-18. hdlc rx fifo function diagram
S3C4530A hdlc contr ollers 8- 47 hdlc brg time constant registers (hbrgtc) table 8-14. hbrgtca and hbrgtcb register registers offset r/w description reset value hbrgtca 0x701c r/w hdlc brg time constant register 0x00000000 hbrgtcb 0x801c r/w hdlc brg time constant register 0x00000000 the hdlc brg time constant register value can be changed at any time, but the new value does not take effect until the next time the constant is loaded into the down counter. no attempt is made to synchronize the loading of the time constant into hbrgtc while the clock is driving the down counter. for this reason, you should first disable the baud rate generator before loading the new time constant into the hbrgtc register. the formula for determining the appropriate time constant for a given baud rate is shown below. the desired rate is shown in bits per second. this formula shows how the counter decrements from n down to zero-plus-one cycles for reloading the time constant. this value is then fed to a toggle flip-flop to generate the square wave output. brgout1 = (mclk2 or rxc) / (cnt0 + 1) / (16 cnt1 ) brgout2 = (mclk2 or rxc) / (cnt0+1) / (16 cnt1 ) / (1 or 16 or 32 according to cnt2 value of the hbrgtc) 31 15 16 [1:0] time constant value for cnt2 00 = divide by 1 01 = adivide by 16 10 = divide by 32 [3:2] time constant value for cnt1 00 = divide by 1 01 = divide by 16 [15:4] time constant value for cnt0 0 18 17 12 13 14 9 10 11 6 7 8 3 4 5 1 2 cnt0 cnt1 19 21 20 cnt2 22 23 24 25 26 27 28 29 30 figure 8-19. hdlc brg time constant register
hdlc controllers s3 c4530a 8 - 48 hdlc preamble constant register (hprmb) the hprmb register is used to meet the dpll requirements for phase-locking. the preamble pattern is transmitted as many tx preamble length bit values in hmode[10:8] when the tx preamble bit (txprmb) is '1', and then the tx preamble bit is cleared automatically. the opening flag follows this preamble pattern, and the data will be transmitted. table 8-15. hprmba and hprmbb register registers offset r/w description reset value hprmba 0x7020 r/w hdlc preamble constant register 0x00000000 hprmbb 0x8020 r/w hdlc preamble constant register 0x00000000 31 15 16 [7:0] preamble pattern 0 18 17 12 13 14 9 10 11 6 7 8 3 4 5 1 2 19 21 20 preamble pattern 22 23 24 25 26 27 28 29 30 figure 8-20. hdlc preamble constant register the reference for the preamble pattern of each data mode is as follows: table 8-16. preamble reference pattern data mode preamble pattern nrz aa nrzi 00 fm0 ff fm1 00 manchester aa
S3C4530A hdlc contr ollers 8- 49 hdlc station address registers (hsadr0-3) and hmask register each hdlc controller has five 32-bit registers for address recognition: four station address registers and one mask register. generally, the hdlc controller reads the address of the frame from the receiver, to check it against the four station address values, and then masks the result with the user-defined hmask register. a "1" in the hmask register represents a bit position for which an address compare should occur. a "0" represents a masked bit position. if you check the address up to four bytes, the hmask register value should be 0xffffffff. dependent on the hmask register value, the frame's address is compared. if the address is not matched, this frame is discarded. table 8-17. hsadr and hmask register registers offset r/w description reset value hsadr0a 0x7024 r/w hdlc station address 0 0x00000000 hsadr1a 0x7028 r/w hdlc station address 1 0x00000000 hsadr2a 0x702c r/w hdlc station address 2 0x00000000 hsadr3a 0x7030 r/w hdlc station address 3 0x00000000 hmaska 0x7034 r/w hdlc address mask register 0x00000000 hsadr0b 0x8024 r/w hdlc station address 0 0x00000000 hsadr1b 0x8028 r/w hdlc station address 1 0x00000000 hsadr2b 0x802c r/w hdlc station address 2 0x00000000 hsadr3b 0x8030 r/w hdlc station address 3 0x00000000 hmaskb 0x8034 r/w hdlc address mask register 0x00000000 note: recognize one 32-bit address and the 32-bit broadcast address hmask hsadr0 hsadr1 hsadr3 hsadr2 hmask hsadr0 hsadr1 hsadr3 hsadr2 0xff000000 0x55xxxxxx 0x55xxxxxx 0x55xxxxxx 0x55xxxxxx note: recognize a single 8-bit address 0xff ff ff ff 0xabcdefgh 0xff ff ff ff 0xabcdefgh 0xabcdefgh figure 8-21. address recognition
hdlc controllers s3 c4530a 8 - 50 31 15 16 station address byte register and mask register 0 18 17 12 13 14 9 10 11 6 7 8 3 4 5 1 2 19 21 20 fourth byte 22 23 24 25 26 27 28 29 30 third byte second byte first byte [31:24] first address byte [23:16] second address byte [15: 8 ] third address byte [ 7 : 0 ] fourth address byte figure 8-22. hdlc station address and hmask register dma tx buffer descriptor pointer register the dma transmit buffer descriptor pointer register contains the address of the tx buffer data pointer on the data to be sent. during a dma operation, the buffer descriptor pointer is updated by the next buffer data pointer. table 8-18. dma tx buffer descriptor pointer registers registers offset r/w description reset value hdmatxptra 0x7038 r/w dma tx buffer descriptor pointer 0xffffffff hdmatxptrb 0x8038 r/w dma tx buffer descriptor pointer 0xffffffff 31 15 16 [25:0] dma tx buffer descriptor pointer 0 18 17 12 13 14 9 10 11 6 7 8 3 4 5 1 2 19 21 20 dma tx buffer descriptor pointer 22 23 24 25 26 27 28 29 30 figure 8-23. dma tx buffer descriptor pointer
S3C4530A hdlc contr ollers 8- 51 dma rx buffer descriptor pointer register the dma receive buffer descriptor pointer register contains the address of the rx buffer data pointer on the data to be received. during a dma operation, the buffer descriptor pointer is updated by the next buffer data pointer. table 8-19. dma rx buffer descriptor pointer registers registers offset r/w description reset value hdmarxptra 0x703c r/w dma rx buffer descriptor pointer 0xffffffff hdmarxptrb 0x803c r/w dma rx buffer descriptor pointer 0xffffffff 31 15 16 [25:0] dma rx buffer descriptor pointer 0 18 17 12 13 14 9 10 11 6 7 8 3 4 5 1 2 19 21 20 dma rx buffer descriptor pointer 22 23 24 25 26 27 28 29 30 figure 8-24. dma rx buffer descriptor pointer maximum frame length register the hdlc controller checks the length of an incoming frame against the user-defined value in dma mode. if the frame received exceeds this register value, the frame is discarded, and flv(frame length violated) bit is set in the buffer descriptor belonging to that frame. table 8-20. hdmatxcnt and hdmarxcnt registers registers offset r/w description reset value hmflra 0x7040 r/w maximum frame length 0xxxxx0000 hmflrb 0x8040 r/w maximum frame length 0xxxxx0000 31 15 16 [15:0] maximum frame length 0 18 17 12 13 14 9 10 11 6 7 8 3 4 5 1 2 19 21 20 maximum frame length 22 23 24 25 26 27 28 29 30 figure 8-25. maximum frame length register
hdlc controllers s3 c4530a 8 - 52 receive buffer size register the rx buffer size register contains the 16-bit user-defined value. this user-defined count value determines the buffer size for one buffer descriptor. if incoming hdlc frame is longer than the rx buffer size register value, the next buffer descriptor having the rx buffer size value will be used. table 8-21. dma rx buffer size register registers offset r/w description reset value hrbsra 0x7044 r/w receive buffer size register 0xxxxx0000 hrbsrb 0x8044 r/w receive buffer size register 0xxxxx0000 31 15 16 [15:0] receive buffer size register 0 18 17 12 13 14 9 10 11 6 7 8 3 4 5 1 2 19 21 20 receive buffer size 22 23 24 25 26 27 28 29 30 figure 8-26. dma receive buffer size register synchronization register the hdlc synchronous register content will be sent during flag idle in hdlc mode. in mark idle mode, this register content can not used. however, in transparent mode with in-line sync, this register value used for searching sync pattern . this sync pattern is used as like opening or closing flag. in-line sync or out-line sync determined by autoen bit value. if autoen bit is set to zero, it is determined to in-line sync in transparent mode. table 8-22. synchronization register registers offset r/w description reset value hsynca 0x7048 r/w hdlc sync register 0x7e hsyncb 0x8048 r/w hdlc sync register 0x7e 31 15 16 [7:0] sync pattern 0 18 17 12 13 14 9 10 11 6 7 8 3 4 5 1 2 19 21 20 sync pattern 22 23 24 25 26 27 28 29 30 figure 8-27. hdlc synchronization register
S3C4530A hdlc contr ollers 8- 53 transparent control register the hdlc transparent register controls the transparent data flow. this is composed with data sampling field and rts control field. table 8-23. transparent control register registers offset r/w description reset value tcona 0x704c r/w transparent control register 0xxxxx0000 tconb 0x804c r/w transparent control register 0xxxxx0000 bit number bit name description [1:0] data sampling (ds) these bit values determine which data bits are regarded as valid after the ndcd state active. 00 = the first valid bit is d4, 01 = the first valid bit is d3, 10 = d2 and 11 = d1. see figure 8-28, data sampling method. [3:2] reserved not applicable. [4] rts control(rts) it this bit set to one, the nrts pin goes low. [31:5] reserved not applicable. data ndcd rxc sampled here if ds value is 01. d1 d2 d3 d4 d5 d6 d7 d8 figure 8-28. data sampling method
hdlc controllers s3 c4530a 8 - 54 tsa configuration register tsa control register handles the interface of hdlcs with the external world. this enables and disables the tsa block, select whether to mux each channel source and determine the data rate on the dcl clock. table 8-24. transparent control register registers offset r/w description reset value tsacfg 0x7800 w tsa configuration register 0x00000000 bit number bit name description [0] tsa enable (tsaen) you can enable the time slot assignor by setting this bit as 1. [1] a mode select (amode) hdlc channel a can be used as a dce mode or pcm highway. if you set this bit, a-channel will be assigned as pcm highway. [2] b mode select(bmode) hdlc channel b can be used as a dce mode or pcm highway. if you set this bit, a-channel will be assigned as pcm highway. [3] clock divide (clkdiv) using this, the data clock (dcl) can be divided by 2. if you set as 1, the data clock will be a rate divided by 2 of the rxc pin. [31:4] reserved not applicable. 31 15 16 [0] tsa enable bit 0 : tsa disable 1 : tsa enable [1] mode selection on the hdlc channel a 0 = dce 1 = pcm highway (non-multiplexed) [2] mode selection on the hdlc channel b 0 = dce 1 = pcm highway (non-multiplexed) [3] clock divide 0 = 1x clock mode 1 = 0.5x clock mode 0 18 17 12 13 14 9 10 11 6 7 8 3 4 5 1 2 19 21 20 22 23 24 25 26 27 28 29 30 t s a e n reserved a m o d e b m o d e c l k d i v figure 8-29. tsa configure register
S3C4530A hdlc contr ollers 8- 55 tsa channel time slot register this time slot register will assign the each tdm channel into the specified period. simply setting the start and the end location, you can load the each channel data through the pcm highway. if the start value is smaller than the end bit, the data will be continued through the two frames until meet the start position. table 8-25. transparent control register registers offset r/w description reset value tsaacfg 0x7804 w tsa a time slot register 0x00000000 tsabcfg 0x7808 w tsa b time slot register 0x00000000 bit number bit name description [11:0] start the location of start bit at which the hdlcx time slot assigned [15:12] reserved not applicable. [27:16] stop the location of (stop+1) bit at which the hdlcx time slot assigned for instance, if you want to stop the tsa at 7-th bit, then you should set it as the value 8. [31:28] reserved not applicable. 31 15 16 [11: 0 ] the location of start bit of the time slot [15:12 ] reserved [27:16 ] the location of stop bit of the time slot [31:28 ] reserved 0 18 17 12 13 14 9 10 11 6 7 8 3 4 5 1 2 19 21 20 22 23 24 25 26 27 28 29 30 reserved stop bit reserved start bit figure 8-30. tsa time slot position register
hdlc controllers s3 c4530a 8 - 56 note: you can refer the application note of s3c4510 on using the hdlc, the general items related on it will not be covere d in this manual. programming guide for transparent mode actually, the every operation in transparent mode is same with the hdlc mode, except that this mode does not compare the starting/closing flag and doesn?t have the zero inserting/deleting feature. that mean you can get higher data rate than hdlc mode, which gives you the merits for sending or receiving the image data or file transfer. definition for transparent mode you can see the definition for the transparent mode in listing 1 listing 1. definition for transparent mode #define setsyncpattern(channel, pattern) hsync(channel) = pattern #define setdatasample(channel, first) tcon(channel) = first transparent mode initialization after finishing the hdlc initialization, you need to set control bits for this mode. step 1. set the txtrans or rxtrans in hmode register. step 2. set the sync type using the autoen bit. step 3. set the sync pattern for finding the start point of frame. step 4. setting the sampling field and rts for external synchronization. listing 2. a part of hdlcinitialize() in transparent mode int hdlcportinit(thdlcdev *hdlc) { ? if(hdlc->txcommmode == comm_mode_trans) hmode(channel) |= txtrans ; if(hdlc->rxcommmode == comm_mode_trans) hmode(channel) |= rxtrans; hcon(channel) &= ~autoen; // autoen = 0 setsyncpattern(channel, 0x7e); setdatasample(channel, firstvalidd4); ? }
S3C4530A hdlc contr ollers 8- 57 inline-synchronization this program sets the in-line synchronization in listing 1. by disabling the autoen in hcon and rts in tcon, the receiver will start to receive the data after searching the sync pattern. external synchronization to use the external synchronization, you need to enabling the autoen in hcon and rts in tcon. after detection dcd, start to receive the receive data. once the reception begins, the transition of dcd pin will be ignored and data can be received until trxstop is set to one by cpu then the new synchronization process begins. transmitting a transparent frame. finishing the intialization, you can send data through transparent channel. only the difference from the hdlc mode, you should give the sync pattern of the receiver side at the first byte of frame. because the transparent mode don?t use the station address, you don?t have to write down the station address on the frame data. listing 3. transmit _frame() ? // step 1. set the sync pattern of the receiver side framebuffer.header.address[0] = 0x7e ; // step 2. fill the any kind of data from the 2 nd byte in frame framebuffer.header.address[1] = 0x12; framebuffer.header.address[2] = 0x34 ; framebuffer.header.address[3] = 0x56 ; framebuffer.header.control[0] = 0x78; for (i=0;i hdlc controllers s3 c4530a 8 - 58 listing 4. hdlccputransrxisr() // step 1. check any received data in fifo if (inthdlcstatus & rxfa) { // step 2. read received data from hdlc receive fifo entry if(!readdatafromfifo(channel,remainbyte)){ // if the ending condition meet, update and assign new buffer // step 3. get current receive buffer descriptor point crxbdptr = (tbuffer descriptor *)gcrxbdptr[channel]; // step 4. clear owner to cpu crxbdptr->bufferdataptr &= bownership_cpu ; // step 5. get length and status crxbdptr->lengthfield = modeintrxdatasize[channel] ; crxbdptr->statusfield = inthdlcstatus ; // step 6. get next buffer descriptor gcrxbdptr[channel] = (u32)crxbdptr->nextbufferdescriptor ; // step 7. initialize hdlc dma for next comming frame cpuhdlcrxinit(channel); } }
S3C4530A hdlc contr ollers 8- 59 listing 5. readdataformfifo() /* * function : readdatafromfifo * description : read frame data from hdlc rx fifo * this function is only used when interrupt mode receive */ int readdatafromfifo(u32 channel, u32 bcnt) { int i, cnt ; u32 *testbuffer; cnt = (int)(((bcnt&~3)+4)/4) ; modeintrxdatasize[channel] += (bcnt+1) ; for (i=0 ; i hdlc controllers s3 c4530a 8 - 60 programming guide for time slot assignor one time-slot-assignor (tsa) is equipped for the flexible control of two hdlcs. you can upload/download data separately to /from each channel through time-slot-assignor. definition for time slot assignor time slot assignor has three registers. you can see the handling of this block is simple. listing 6. definition for time slot assignor /**************************************************/ /* s32c4530 : tsa registers */ /**************************************************/ #define tsacon (vpint(base_addr+0x7800)) #define tsaslot(channel) (vpint(base_addr+0x7804+ channel*4)) time slot assignor initialisation before starting the hdlc initialisation, you need to set tsa registers. [note] you do not initialise tsa after hdlc registers initialisation, if you do, hdlc registers will be crashed by writing any data into tsa registers. and the tsa registers are write-only, if you read, the value is not what you write. whenever you want to change even only one of tsa registers, you should re-initialise the hdlc after changing. step 1. check whether the external-interface is correct for pcm mode in table 8-3. ( fsc : txc pin , dcl : rxc pin) step 2. set the tsa configuration register for each channel step 3. set the tsa channel time slot registers for the slot time-window. step 4. initialising the hdlc as external clock use. listing 7. tsainitialize() int tsainitialize(thdlcdev *hdlc) { u8 channel; u16 start[2] = {starta,startb}; u16 stop[2] = {stopa,stopb}; hdlc->txclk = txctxc ; hdlc->rxclk = rxcrxc ; tsacon = tsaen | pcma | pcmb ; for(channel = tsaa; channel<=tsab;channel++) tsaslot(channel) = start[channel] | (stop[channel] <<16); }
S3C4530A hdlc contr ollers 8- 61 how to writing the tsa time slot position registers when you set the time slot position, you need to know the internal slot window operation. internally the number of clocks during fsc one-cycle is the starting value of slot cnt after fsc rising edge and the value one is followed. so if the fsc has 8-clock and you want to window the time slot from first to third dcl clock, then you can set as figure 8-31. note: you should take caution on setting this registers by checking the outer signals like txd and rxd pin. and the txd pin will be high-impedance (floating) outside the time window. slot cnt time slot dcl [rxc] fsc [txc] 8 1 2 3 4 5 6 7 slot open when you set the followin values. #define start 8 #defin stop 3 tsaslot(channel) = start | (stop<<16) figure 8-31. tsa time slot tsa operation after finishing the tsa and hdlc initialization, you can send/receive data through hdlc channel a. the operation scheme is same with the hdlc and transparent mode. so you can use the same functions for sending and receiving.
hdlc controllers s3 c4530a 8 - 62 notes
S3C4530A dma contro ller 9- 1 9 dma controller overview the S3C4530A has a two-channel general dma controller, called the gdma. the two-channel gdma performs the following data transfers without cpu intervention: ? memory-to-memory (memory to/from memory) ? uart-to-memory (serial port to/from memory) the on-chip gdma can be started by software and/or by an external dma request (nxdreq). software can also be used to restart a gdma operation after it has been stopped. cpu can recognize when a gdma operation has been completed by software polling and/or when it receives an appropriate internally generated gdma interrupt. the S3C4530A gdma controller can increment or decrement source or destination addresses and conduct 8-bit (byte), 16-bit (half-word), or 32-bit (word) data transfers. system bus gdma channel 0 ndreq ndack gdma channel 1 ndreq port 14 data gdma iopcon [27:26] nxdack 0 iopcon [29:28] nxdack 1 port 15 data gdma mode selection mode selection nxdreq 1 uart1 uart0 nxdreq 0 ndack figure 9-1. gdma controller block diagram
dma controller s3c4 530a 9- 2 gdma special registers table 9-1. gdma special registers overview registers offset r/w description reset value gdmacon0 0xb000 r/w gdma controller channel 0 control register 0 00000000 gdmacon1 0xc000 r/w gdma controller channel 1 control register 0 00000000 gdmasrc0 0xb004 r/w gdma channel 0 source address register undefined gdmadst0 0xb008 r/w gdma channel 0 destination address register undefined gdmasrc1 0xc004 r/w gdma channel 1 source address register undefined gdmadst1 0xc008 r/w gdma channel 1 destination address register undefined gdmacnt0 0xb00c r/w gdma channel 0 transfer count register undefined gdmacnt1 0xc00c r/w gdma channel 1 transfer count register undefined gdma control registers table 9-2. gdmacon0 and gdmacon1 registers registers offset r/w description reset value gdmacon0 0xb000 r/w gdma controller channel 0 control register 0 00000000 gdmacon1 0xc000 r/w gdma controller channel 1 control register 0 00000000 table 9-3. gdma control register description bit number bit name reset value [0] run enable/disable setting this bit to "1", starts a dma operation. to stop dma, you must clear this bit to "0". you can use the gma run bit control address (gdmacon offset address + 0x20) to manipulate this bit. by using the run bit control address, other gdma control register values are not affected. [1] busy status when dma starts, this read-only status bit is automatically set to "1". when it is "0", dma is idle. [3:2] gdma mode selection four sources can initiate a dma operation: 1) software (memory- to-memory), 2) an external dma request (nxdreq), 3) the uart0 block, and 4) the uart1 block. the mode selection setting determines which source can initiate a dma operation at any given time. [4] destination address direction this bit controls whether the destination address will be decremented ("1") or incremented ("0") during a dma operation. [5] source address direction this bit controls whether the source address will be decremented ("1") or incremented ("0") during a dma operation.
S3C4530A dma contro ller 9- 3 table 9-3. gdma control register description (continued) bit number bit name reset value [6] destination address fix this bit determines whether or not the destination address will be changed during a dma operation. you use this feature when transferring data from multiple sources to a single destination. [7] source address fix this bit determines whether or not the source address will be changed during a dma operation. you use this feature when transferring data from a single source to multiple destinations. [8] stop interrupt enable to start/stop a dma operation, you set/clear the run enable bit. if the stop interrupt enable bit is "1" when dma starts, a stop interrupt is generated when dma operation stops. if this bit is "0", the stop interrupt is not generated. [9] four-data burst enable if this bit is set to one, gdma operates under 4-data burst mode. under the 4-data burst mode, 4 consecutive source addresses are read and then are written to the consecutive destination addresses. if 4-data burst mode is set to one, "transfer count register" should be set carefully because the 4-data burst move is executed during decreasing of the transfer count. the 4-data burst mode can be used only when gmda mode is software or external dma request mode. [10] peripheral direction this bit is used to specify the direction of a dma operation when the mode bits [3:2] are set to '10' (uart0 from/to memory) or '11' (uart1 from/to memory). if this bit is "1", dma operates in the memory-to-peripheral direction (e.g., to the parallel port or uart). when it is "0", dma operates in the peripheral-to-memory direction. [11] single/block mode this bit determines the number of external dma requests (nxdreqs) that are required for a dma operation. in single mode, when [11] = "0", the S3C4530A requires an external dma request for every dma operation. in block mode, when [11] = "1", the S3C4530A requires only one external dma request during the entire dma operation. an entire dma operation is defined as the operation of dma until the counter value is zero. note: you should not use block mode together with demand mode, or single mode in conjunction with continuous mode. [13:12] transfer width these bits determine the transfer data width to be one byte, one half-word, or one word. if you select a byte transfer operation, the source/destination address will be incremented or decremented by one with each transfer. each half-word transfer increments or decrements the address by two, and each word transfer by four.
dma controller s3c4 530a 9- 4 table 9-3. gdma control register description (continued) bit number bit name reset value [14] continuous mode this bit lets the dma controller hold the system bus until the dma transfer count value is zero. you must therefore manipulate this bit carefully so that dma transfer operations do not exceed a acceptable time interval (as, for example, in a dram refresh operation). note: you can use continuous mode together with a software request mode. [15] demand mode setting this bit speeds up external dma operations. when [15]="1", the dma transfers data when the external dma request signal (nxdreq) is active. the amount of data transferred depends on how long nxdreq is active. when nxdreq is active and dma gets the bus in demand mode, dma holds the system bus until the nxdreq signal becomes non-active. therefore, the period of the active nxdreq signal should be carefully timed so that the entire operation does not exceed an acceptable interval (as, for example, in a dram refresh operation). note: in demand mode, you must clear the single/block and continuous mode control bits to "0". note : to ensure the reliability of dma operations, the gdma control register bits must be configured independently and carefully.
S3C4530A dma contro ller 9- 5 [0] run enable (re) 0 = disable dma operation 1 = enable dma operation [1] busy status (bs) 0 = dma is idle 1 = dma is active [3:2] mode selection (mode) 00 = software mode (memory to memory) 01 = external extdreq mode (for external devices) 10 = uart0 block 11 = uart1 block [4:] destination address direction (da) 0 = increase source address 1 = decrease source address [5] source address direction (sa) 0 = increase source address 1 = decrease source address [6] destination address fix (df) 0 = increase/decrease destination address 1 = do not change destination address (fix) [7] source address fix (sf) 0 = increase/decrease source address 1 = do not change source address (fix) [8] stop interrupt enable (si) 0 = do not generate a stop interrupt when dma stops 1 = generate a stop interrupt when dma stops [9] four-data burst enable (fb) 0 = disable 4-data burst mode 1 = enable 4-data burst mode [10] transfer direction (for uart0/uart1 only) (td) 0 = uart0/uart1 to memory 1 = memory to uart0/uart1 [11] single/block mode (sb) 0 = one nxdreq initiates a single dma operation 1 = one nxdreq initiates a whole dma operation [13:12] transfer width (tw) 00 = byte (8 bits) 01 = half-word (16 bits) 10 = word (32 bits) 11 = no use [14] continuous mode (cn) 0 = normal operation 1 = hold system bus until the whole dma operation stops [15] demand mode (dm) 0 = normal external dma mode 1 = demand mode r e b s m o d e d a s a d f s f s i f b t d s b t w c n d m 31 16 13 12 11 10 9 8 7 6 5 4 3 2 1 0 14 15 figure 9-2. gdma control register
dma controller s3c4 530a 9- 6 gdma source/destination address registers the gdma source/destination address registers contain the 26-bit source/destination addresses for gdma channels 0 and 1. depending on the settings you make to the gdma control register (gdmacon), the source or destination addresses will either remain the same, or they will be incremented or decremented. table 9-4. gdamsrc0/1 and gdmadst0/1 registers registers offset r/w description reset value gdmasrc0 0xb004 r/w gdma channel 0 source address register undefined gdmadst0 0xb008 r/w gdma channel 0 destination address register undefined gdmasrc1 0xc004 r/w gdma channel 1 source address register undefined gdmadst1 0xc008 r/w gdma channel 1 destination address register undefined 31 26 25 0 source/destination address [25:0] source/destination address figure 9-3. gdma source/destination address register
S3C4530A dma contro ller 9- 7 dma transfer count registers the dma transfer count registers contain the 24-bit current count value of the number of dma transfers completed for gdma channels 0 and 1. the count value is always decremented by one for each completed dma operation, regardless of the gdma data transfer width or four-data burst mode. note at the 4-data burst mode, actual transfer data size will be "transfer count x4." table 9-5. gdmacnt0/1 registers registers offset r/w description reset value gdmacnt0 0xb00c r/w gdma channel 0 transfer count register undefined gdmacnt1 0xc00c r/w gdma channel 1 transfer count register undefined 31 24 23 0 transfer count [23:0] transfer count figure 9-4. dma transfer count register
dma controller s3c4 530a 9- 8 gdma function description the following sections provide a functional description of the gdma controller operations. gdma transfers the gdma transfers data directly between a requester and a target. the requester and target are memory, uart or external devices. an external device requests gdma service by activating nxdreq signal. a channel is programmed by writing to registers which contain requester address, target address, the amount of data, and other control contents. uart, external i/o, or software(memory) can request gdma service. uart is internally connected to the gdma. starting/ending gdma transfers gdma starts to transfer data after the gdma receives service request from nxdreq signal, uart, or software. when the entire buffer of data has been transferred, the gdma becomes idle. if you want to perform another buffer transfer, the gdma must be reprogrammed. although the same buffer transfer will be performed again, the gdma must be reprogrammed. data transfer modes single mode a gdma request (nxdreq or an internal request) causes one byte, one half-word, or one word to be transmitted if 4-data burst mode is disable state, or four times of transfer width if 4-data burst mode is enable state. single mode requires a gdma request for each data transfer. the nxdreq signal can be de-asserted after checking that nxdack has been asserted. nxdreq nxdack rd/wr cycle figure 9-5. external dma requests (single mode)
S3C4530A dma contro ller 9- 9 block mode the assertion of only one gdma request (nxdreq or an internal request) causes all of the data, as specified by the control register settings, to be transmitted in a single operation. the gdma transfer is completed when the transfer counter value reaches zero. the nxdreq signal can be de-asserted after checking that nxdack has been asserted. nxdreq nxdack rd/wr cycle figure 9-6. external dma requests (block mode) demand mode in demand mode, the gdma continues transferring data as long as the gdma request input (nxdreq) is held active. nxdreq nxdack rd/wr cycle figure 9-7. external dma requests (demand mode)
dma controller s3c4 530a 9- 10 temrs setup time temrh hold time temaf delay (falling) temar delay (rising) 5.8 ns worst best 0 ns 28.64 ns 13.29 ns 21.9 ns 9.68 ns nxdreq nxdack temrs temrh temaf temar min.3 cycles mclko figure 9-9. external dma requests detailed timing (S3C4530A)
S3C4530A dma contro ller 9- 11 clock description the internal clock(in_mclk; this is the operating clock on the S3C4530A) differs from mclko(pad out clock). for more clear description, internal clock(in_mclk) is used at this timing diagram. following figure 9-9 is the relationship of internal clock(in_mclk) and mclko(pad out clock). you must think one more step that is the concern with mclko. temrs setup time temrh hold time temaf delay (falling) temar delay (rising) 5.8 ns worst best 0 ns 28.64 ns 13.29 ns 21.9 ns 9.68 ns nxdreq nxdack temrs temrh temaf temar min.3 cycles mclko figure 9-10. mclko and sclk (in_mclk)
dma controller s3c4 530a 9- 12 single and one data burst mode (gdmacon[11] = 0, [9] = 0 ) dreq and dack signals are active low. notes: 1. in this region, dma operation is independent of the number of dreq signal pulse. for example, although dreq signal pulses 3 times in the region, gdmac transfers data only one time from source address to destination address. current dreq signal is idle state(deasserted) when dack siganl is idle state (high). otherwise, gdmac recognizes current dreq signal as next one and transfers next data. i recommand that dreq signal is deasserted when dack signal is active. 2. is three more cycles(3+a cycles). the 'a' is internal system bus acquistion time. 3. signal falls at negative edge in_mclk clock after source data is valid. in_mclk dreq source address destination address source data destination data recommand deasserted time dack address data b c a figure 9-11. single and one data burst mode timing
S3C4530A dma contro ller 9- 13 single and four data burst mode (gdmacon[11] = 0, [9] = 1 ) dreq & dack signals are active low. in the four data burst mode, gdma count register(gdma cnt) value decreases by 1 after 4 data transfer. notes: 1. in this region, dma operation is independent of the number of dreq signal pulse. for example, although dreq signal pulses 3 times in the region, gdmac transfers data only one time from source address to destination address. current dreq signal is idle state(deasserted) when dack siganl is idle state (high). otherwise, gdmac recognizes current dreq signal as next one and transfers next data. i recommand that dreq signal is deasserted when dack signal is active. 2. is three more cycles(3+a cycles). the 'a' is internal system bus acquistion time. 3. signal falls at negative edge in_mclk clock after source data is valid. in_mclk dreq source address destination address source data destination data recommand deasserted time dack address data b c a figure 9-12. single and four data burst mode timing
dma controller s3c4 530a 9- 14 block and one data burst mode (gdmacon[11] = 1, [9] = 0 ) dreq and dack signals are active low. gdmac transfers data from dreq signal is active till gdma count register consumes. in_mclk dreq recommand deasserted time dack address data source address destination address source address destination address source data destination data source data destination data a note: is in the block mode, gdmac starts to operate with first dreq signal. so in the ideal case, gdmac don't care the number of dreq signal pulse. but i recommand that dreq siganl is deasserted when dack signal is active state. figure 9-13. block and one data burst mode timing block and four data burst (gdmacon[11] = 1, [9] = 1) this timing diagram is the same with single and one data burst exception four data burst. one data burst; source address0 and source data0 ? destination address0 and destination data0 ? .... four data burst; source address0 and source data0 ? source address1 and source data1 ? source address2 and source data2 ? source address3 and source data3 ? destination address0 and destination data0 ? destination address1 and destination data1 ? destination address2 and destination data2 ? destination address3 and destination data3 ? source address4 and source data4 ? .... note in the four data burst mode, gdma count register value decreases by 1 after 4 data transfer.
S3C4530A dma contro ller 9- 15 continuous and one burst mode (gdmacon[14] = 1, [9] = 0 ) dreq and dack signals are active low. in_mclk dreq recommand time dack address data s0 d0 s1 d1 s2 d2 s3 d3 gdma cnt note: s# is source address#, and d# is destination address#. 8 7 6 5 4 3 2 1 0 figure 9-14. continuous and one burst mode timing continuous and four data burst mode (gdmacon[14] = 1, [9] = 1 ) this timing diagram is the same with continuous and one data burst exception four data burst. one data burst; source address0 and source data0 ? destination address0 and destination data0 ? source address1 and source data1 ? destination address1 and destination data1 ? ... four data burst; source address0 and source data0 ? source address1 and source data1 ? source address2 and source data2 ? source address3 and source data3 ? destination address0 and destination data0 ? destination address1 and destination data1 ? destination address2 and destination data2 ? destination address2 and destination data2 ? destination address3 and destination data3 ? ... note in the four data burst mode, gdma count register value decreases by 1 after 4 data transfer.
dma controller s3c4 530a 9- 16 demand and one data burst mode (gdmacon[15] = 1, [9] = 0 ) dreq and dack signals are active low. in_mclk dreq dack address data s0 d0 s1 d1 s2 d2 gdma cnt note: s# is source address#, and d# is destination address#. if gdma cnt is zero, gdmac do not transfer data although dreq signal asserted. 8 7 6 5 4 3 2 1 0 s3 d3 figure 9-15. demand and one data burst mode timing demand & four data burst mode ( gdmacon[15] = 1, [9] = 1 ) this timing diagram is the same with demand & one data burst exception four data burst. one data burst; source address0 and source data0 ? destination address0 and destination data0 ? ... four data burst; source address0 and source data0 ? source address1 and source data1 ? source address2 and source data2 ? source address3 and source data3 ? destination address0 and destination data0 ? destination address1 and destination data1 ? destination address2 and destination data2 ? destination address2 and destination data2 ? destination address3 and destination data3 ? ... note if you want to use continuous mode, you must set block mode not single mode. if you want to use demand mode, you must set single mode not block mode.
S3C4530A uart 10- 1 10 serial i/o (uart) overview the S3C4530A uart (universal asynchronous receiver/transmitter) unit provides two independent asynchronous serial i/o (sio) ports. each port can operate in interrupt-based or dma-based mode. that is, the uart can generate internal interrupts or dma requests to transfer data between the cpu and the serial i/o ports. the most important features of the S3C4530A uart include: ? programmable baud rates ? 32-byte transmit fifo and 32-byte receive fifo ? uart source clock selectable (internal clock : mclk2, external clock : euclk) ? infra-red (ir) transmit/receive ? insertion of one or two stop bits per frame ? selectable 5-bit, 6-bit, 7-bit, or 8-bit data transfers ? parity checking each sio unit has a baud rate generator, transmitter, receiver, and a control unit, as shown in figure 10-1. the baud-rate generator can be driven by the internal system clock, mclk, or by the external clock, uclk. auto baud rate generator try to get the baud rate from input data in this mode. the transmitter and receiver blocks have independent data buffer registers and data shifters. and 32-byte transmit fifo and 32-byte receive fifo is also provided which include transmit and receive buffer. in non-fifo mode, transmit data is written first to the transmit buffer register. from there, it is copied to the transmit shifter and then shifted out by the transmit data pin, uatxdn. receive data is shifted in by the receive data pin, uarxdn. it is then copied from the shifter to the receive buffer register when one data byte has been received. otherwise, you can select fifo mode. in fifo mode, transmit and receive use transmit fifo and receive fifo, instead of tx/ rx buffer register. they are controlled by each fifo trigger level. the sio control units provide software controls for mode selection, and for status and interrupt generation. in S3C4530A, software flow control or hardware flow control can be selected according to the application. to use modem interface signal, see chapter 12 iopcon1 register.
uart S3C4530A 10- 2 control and status block baudrate generator and detector modem control signal txbuffer register -------------- transmit fifo (32 bytes) transmit shift register rxbuffer register -------------- receiver fifo (32 bytes) receiver shift register ir tx encoder ir rx decoder 1 0 uart txdn uart rxdn uclk baud rate divisor transmit data receive data transmit control receive control receive status transmit status control character register uart_clk mclk2 ucon : uclk ucon : ir system bus 0 1 0 1 figure 10-1. serial i/o block diagram
S3C4530A uart 10- 3 uart special registers table 10-1. uart special registers overview register offset address r/w description reset value ucon0 0xd000 r/w uart0 control register 0x00 ucon1 0xe000 r/w uart1 control register 0x00 ustat0 0xd004 r/w uart0 status register 0xe0240 ustat1 0xe004 r/w uart1 status register 0xe0240 uinten0 0xd008 r/w uart0 interrupt enable register 0xc0 uinten1 0xe008 r/w uart1 interrupt enable register 0xc0 utxbuf0 0xd00c w uart0 transmit buffer register 0xxx utxbuf1 0xe00c w uart1 transmit buffer register 0xxx urxbuf0 0xd010 r uart0 receive buffer register 0xxx urxbuf1 0xe010 r uart1 receive buffer register 0xxx ubrdiv0 0xd014 r/w uart0 baud rate divisor register 0x00 ubrdiv1 0xe014 r/w uart1 baud rate divisor register 0x00 conchar1_0 0xd018 r/w uart0 control character register 1 0x00 conchar1_1 0xe018 r/w uart1 control character register 1 0x00 conchar2_0 0xd01c r/w uart0 control character register 2 0x00 conchar2_1 0xe01c r/w uart1 control character register 2 0x00
uart S3C4530A 10- 4 uart control registers table 10-2. ucon0 and ucon1 registers registers offset address r/w description reset value ucon0 0xd000 r/w uart0 control register 0x00 ucon1 0xe000 r/w uart1 control register 0x00 table 10-3. uart control register description bit number bit name reset value [1:0] transmit mode (tmode) this two-bit value determine which function is currently able to write tx data to the uart transmit buffer register, utxbuf. 00 = disable tx mode. 01 = interrupt request 10 = gdma ch 0 request 11 = gdma ch 1 request [3:2] receive mode (rmode) this two-bit value determine which function is currently able to write tx data to the uart transmit buffer register, utxbuf. 00 = disable rx mode. 01 = interrupt request 10 = gdma ch 0 request 11 = gdma ch 1 request [4] send break (sbr) set this bit to one to cause the uart to send a break. if this bit value is zero, a break does not send. a break is defined as a continuous low level signal on the transmit data output with the duration of more than one frame transmission time. [5] serial clock selection (uclk) this selection bit specifies the clock source. 0 = internal (mclk2) 1 = external (uclk) [6] auto baud rate detect (abrd) setting this bit causes the uart to enter auto baud rate detect mode. in this mode, uart try to get the baud rate from input data. [7] look-back mode (loopb) setting this bit causes the uart to enter loop-back mode. in loop-back mode, the transmit data output is sent high level and the transmit buffer register, utxbuf, is internally connected to the receive buffer register, urxbuf. note: this mode is provided for test purposes only. for normal operation, this bit should always be "0". [10:8] parity mode (pmd) the 3-bit parity mode value specifies how parity generation and checking are to be performed during uart transmit and receive operations: 0xx = no parity 100 = odd parity 101 = even parity 110 = parity is forced/checked as a "1" 111 = parity forced/checked as a "0". [11] number of stop bits (stb) this bit specifies how many stop bits are used to signal end-of- frame (eof) : 0 = one stop bit per frame 1 = two stop bit per frame
S3C4530A uart 10- 5 table 10-3. uart control register description (continued) bit number bit name reset value [13:12] word length (wl) this two bit word length value indicates the number of data bits to be transmitted or received per frame : 00 = 5bits 01 = 6bits 10 = 7bits 11 = 8bits [14] infra-red mode (ir) the S3C4530A uart block supports infra-red (ir) transmit and receive operations. in ir mode, the transmit period is pulsed at a rate of 3/16 that of the normal serial transmit rate (when the transmit data value in the utxbuf register is zero). to enable ir mode operation, you set ulcon[7] to "1". otherwise, the uart operates in normal mode. in ir receive mode, the receiver must detect the 3/16 pulsed period to recognize a zero value in the receiver buffer register, urxbuf, as the ir receive data. when this bit is "0", normal uart mode is selected. when it is "1", infra-red tx/rx mode is selected. [15] reserved this bit should be cleared by zero. [16] transmit fifo enable (tfen) S3C4530A uart block support 32 byte fifo. if this bit set to one, transmit data moved to tx fifo and then sent. [17] receive fifo enable (rfen) S3C4530A uart block support 32 byte fifo. if this bit set to one, receive data moved to rx fifo. [18] transmit fifo reset (tfrst) if this bit set to one, transmit fifo will be reset. in this case, if there is data in transmit shift register, it will be sent. [19] receive fifo reset (rfrst) if this bit set to one, receive fifo will be reset. in this case, if there is data in receive shift register, it will be received. [21:20] transmit fifo trigger level (tftl) this two bit trigger level value determines when the transmitter start to transmit data in 32-byte transmit fifo : 00 = 30-byte empty/32-byte 01 = 24/32 10 = 16/32 11 = 8/32 [23:22] receive fifo trigger level (tftl) this two bit trigger level value determines when the receiver start to move the received data in 32-byte receive fifo : 00 = 1-byte vaild/32-byte 01 = 8/32 10 = 18/32 28 = 8/32 [24] data terminal ready to pin (dtr) this bit directly controls the nuadtr pin. setting this bit to one, the nuadtr pin goes to low level. if you set this bit to zero, it goes high level. [25] request to send to pin (rts) this bit directly controls the nuarts pin only when the uart is not hardware flow control mode. if this bit set to one, nuarts pin goes low level. otherwise, it remains high level. [27:26] reserved this bit should be cleared by zero.
uart S3C4530A 10- 6 table 10-3. uart control register description (continued) bit number bit name reset value [28] hardware flow control enable (hfen) this bit determines whether uart select hardware flow control or not. if this bit set to one, uart will control all pins concerning to hardware flow control. this pins are ncts, ndcd and nrts. [29] software flow control enable (sfen) this bit determines whether uart select software flow control or not. if this bit set to one, uart will act in software flow control. in this mode, you have to use control character register. [31:30] reserved this bit should be cleared by zero.
S3C4530A uart 10- 7 [1:0] sio transmit mode selection (tmode) 00 = disable 01 = interrupt request 10 = gdma channel 0 request 11 = gdma channel 1 request [3:2] sio receive mode selection (rmode) 00 = disable 01 = interrupt request 10 = gdma channel 0 request 11 = gdma channel 1 request [4] send break (sbr) 0 = normal txdata send 1 = send break signal [5] serial clock selection (cksl) 0 = internal systen clock divided 2 (mclk2) 1 = external uart clock (uclk) [6] auto baud rate detect (aubd) 0 = normal operating mode. 1 = auto baud rate detect mode [7] loopback mode (loob) 0 = normal operating mode. 1 = enable loopback mode (only for test) [10:8] parity mode (pmd) 0xx = no parity. 100 = odd parity. 101 = even parity. 110 = parity forced/checked as 1 111 = parity forced/checked as 0 [11] stop bits (stb) 0 = 1 stop bit 1 = 2 stop bits. [13:12] word length (wl) 00 = 5-bit 01 = 6-bit 10 = 7-bit 11 = 8-bit [14] infra-red mode (ir) 0 = normal operating mode. 1 = infrared tx/rx mode [15] reserved (this bit should be cleared) h f e n c k s l s b r r t s d t r r f t l t f t l w l r f r s t t f r s t r f e n t f e n p m d l o o b a u b d s t b r m o d e t m o d e i r s f e n 31 0 3 4 5 1 2 30 29 28 27 26 25 23 22 20 19 15 14 10 9 24 21 18 17 16 13 12 11 8 7 6 figure 10-2. uart control register
uart S3C4530A 10- 8 [16] transmit fifo enable (tfen) 0 = disable transmit fifo 1 = enable transmit fifo [17] receive fifo enable (rfen) 0 = disable receive fifo 1 = enable receive fifo [18] tranmit fifo reset (tfrst) 0 = normal operation 1 = reset transmit fifo [19] receive fifo reset (rfrst) 0 = normal operation 1 = reset receive fifo [21:20] transmit fifo trigger level (tftl) 00 = 30/32 byte data 01 = 24/32 byte data 10 = 16/32 byte data 11 = 8/32 byte data (empty tx data / txfifo depth) [23:22] receive fifo trigger level (rftl) 00 = 1/32 byte data 01 = 8/32 byte data 10 = 18/32 byte data 11 = 28/32 byte data (valid rx data / rxfifo depth) [24] data terminal ready to pin (dtr) 0 = ndtr goes high level. 1 = ndtr goes low level. [25] request to send to pin (rts) 0 = nrts goes high level. 1 = nrts goes low level. [27:26] reserved (this bit should be cleared) [28] hardware flow control enable (hfen) 0 = disable hardware flow control. 1 = enable hardware flow control. [29] software flow control enable (sfen) 0 = disable software flow control. 1 = enable software flow control. [31:30] reserved (this bit should be cleared) h f e n c k s l s b r r t s d t r r f t l t f t l w l r f r s t t f r s t r f e n t f e n p m d l o o b a u b d s t b r m o d e t m o d e i r s f e n 31 0 3 4 5 1 2 30 29 28 27 26 25 23 22 20 19 15 14 10 9 24 21 18 17 16 13 12 11 8 7 6 figure 10-2. uart control register (continued)
S3C4530A uart 10- 9 uart status registers table 10-4. ucon0 and ucon1 registers registers offset address r/w description reset value ustat0 0xd004 r/w uart0 status register 0xe0240 ustat1 0xe004 r/w uart1 status register 0xe0240 table 10-5. uart control register description bit number bit name reset value [0] receive data valid (rdv) this bit automatically set to one when receive fifo-top or urxbuf contains a valid data received over the serial port. the received data can be read from receive fifo-top or urxbuf . when this bit is "0", there is no valid data. according to the current setting of the uart receive mode bits, an interrupt or dma request is generated when ustat[0] is "1". in case of ucon[3:2]='01' and uinten[0]=1,interrupt requested, and ucon[3:2]='10' or '11', dma request occurred. you can clear this bit by reading receive fifo or urxbuf. note : whether receive fifo top or urxbuf is depends on the ucon[17] rfen. [1] break signal detected (bsd) this bit automatically set to one to indicate that a break signal has been received in receive fifo-top or urxbuf. if the bsd interrupt enable bit, uinten[1], is "1", a interrupt is generated when a break occurs. you can clear this bit by writing '1' to this bit. [2] frame error (fer) this bit automatically set to "1" whenever a frame error occurs during a serial data receive operation. a frame error occurs when a zero is detected instead of the stop bit(s). if the fer interrupt enable bit, uinten[2], is "1", a interrupt is generated when a frame error occurs. you can clear this bit by writing '1' to this bit. [3] parity error (per) this bit automatically set to "1" whenever a parity error occurs during a serial data receive operation. if the per interrupt enable bit, uinten[3], is "1", a interrupt is generated when a parity error occurs. you can clear this bit by writing '1' to this bit.
uart S3C4530A 10- 10 table 10-5. uart control register description (continued) bit number bit name reset value [4] overrun error (oer) this bit automatically set to "1" whenever an overrun error occurs during a serial data receive operation. when urxbuf has a previous valid data, but a new received data is going to be written into urxbuf during non-fifo mode and when a new received data is going to be written into rxfifo with fifo full during fifo mode. ustat[4] is set to '1'. if the oer interrupt enable bit, uinten[4], is "1", a interrupt is generated when a overrun error occurs. you can clear this bit by writing '1' to this bit. [5] control character detect (ccd) ustat[5] is automatically set to "1" to indicate that a control character has been received. if the ccd interrupt enable bit, uinten[5], is "1", an interrupt is generated when a control character is detected. you can clear this bit by writing '1' to this bit. [6] data carrier detect (dcd) this bit set to 1 if nuadcd pin is high at the time uart receiver checks a newly received data whether the data is good frame or not. if the dcd interrupt enable bit, uinten[6], is "1", a interrupt is generated when a data carrier is detected. this bit can be used for error check bit in hardware flow control mode. [7] receive fifo data trigger level reach (rfrea) in receive fifo mode, this bit indicate receive fifo has valid data and reach rx trigger level. so uart request dma to move data in receive fifo. in non-fifo mode, if urxbuf has a received data , this bit is set to '1' also, an interrupt or dma request is generated when ustat[7] is "1". in case of ucon[3:2]='01' and uinten[7]=1,interrupt requested, and ucon[3:2]='10' or '11', dma request occurred. you can clear this bit by reading receive fifo or urxbuf with a good data. if any error, this bit is cleared by writing '1' to corresponding error bit in ustat register. [8] receive fifo empty (rfemt) this bit is only for cpu to monitor uart. when receive fifo is empty, this bit is set to '1'. after reset, default value is '1' . [9] receive fifo full (rfful) this bit is only for cpu to monitor uart. when receive fifo is full, this bit is set to '1'. after reset, default value is '0' [10] receive fifo overrun (rfov) this bit is set to '1' when receive fifo overrun occurs during the receive fifo mode. you can clear this bit by writing '1' to this bit. [11] receiver in idle (ridle) this bit is only for cpu to monitor uart. the rxidle status bit indicates that the inactive state of rxdata.
S3C4530A uart 10- 11 table 10-5. uart control register description (continued) bit number bit name reset value [12] receive event time out ( e_rxto) during receive fifo mode, if there is a valid data in urxfifo or receive fifo within a promised time internal which is determined according to wl(word length) , this bit is set to '1' . urxfifo is for non-fifo mode and receive fifo is for fifo mode. if the e_rxto interrupt enable bit, uinten[12], is "1", an interrupt is generated when a receive event time out is detected and valid data reside in urxbuf or receive fifo. you can clear this bit by writing '1' to this bit. note : event time = wl*4 +12 this bit set to one when the rx data resides in rxfifo. [13] reserved not applicable. [14] data set ready (dsr) this bit is only for cpu to monitor uart. when nuadsr level is low , this bit is set. and nuadsr high, this bit is cleared. [15] clear to send (cts) this bit is only for cpu to monitor uart. when nuacts level is low , this bit is set. and nuacts high, this bit is cleared. [16] cts event occurred (e_cts) this bit is set to '1' whenever nucts level changed. if the e_cts interrupt enable bit, uinten[16], is "1", a interrupt is generated when a cts event is occurred. you can clear this bit by writing '1' to this bit. [17] transmit complete (tc) this bit is only for cpu to monitor uart. ustat[17] is automatically set to "1" when the transmit holding register has no valid data to transmit and when the tx shift register is empty. after reset , default value is '1' [18] transmit holding register empty (the) in transmit fifo mode, when transmit fifo is empty to trigger level, this bit set to '1'. in non-fifo mode, when utxbuf is empty without regarding tx shift register , this bit set to '1'. an interrupt or dma request is generated when ustat[18] is "1". in case of ucon[1:0]='01' and uinten[18]=1, an interrupt requested, and ucon[1:0]='10' or '11', dma request occurred. you can clear this bit by writing txdata into utxbuf or transmit fifo. [19] transmit fifo empty (tfemt) this bit is only for cpu to monitor uart. when transmit fifo is empty, this bit is set to '1'. after reset, default value is '1' [20] transmit fifo full (tfful) this bit is only for cpu to monitor uart. when transmit fifo is full, this bit is set to '1'. after reset, default value is '0' . [31:21] reserved not applicable.
uart S3C4530A 10- 12 [0] receive data valid (rdv) 0 = no valid data (receive fifo top or urxbuf) 1 = valid data present (receive fifo top or urxbuf) [1] break signal deteced (bkd) 0 = no break signal (receive fifo top or urxbuf) 1 = break received [2] frame error (fer) 0 = no frame error (receive fifo top or urxbuf) 1 = frame error occured [3] parity error (per) 0 = no frame error (receive fifo top or urxbuf) 1 = frame error occured [4] overrun error (oer) 0 = no overrun error (receive fifo top or urxbuf) 1 = overrun error occured [5] control character detect (ccd) 0 = no control character (receive fifo top or urxbuf) 1 = control character present (receive fifo top or urxbuf) [6] data carrier detect lost (dcdl) 0 = dcd pin (nudcd) is low at the recever checking time. 1 = dcd pin (nudcd) is high at the recever checking time. [7] receive fifo data trigger level reach (rfrea) 0 = no valid data in urxbuf or not reached to trigger level. 1 = in rxfifo mode, rxfifo has valid data and reach trigger level. in non-fifo mode, urxbuf has valid data. [8] receive fifo empty (rfemt) 0 = receive fifo is not empty 1 = receive fifo is empty [9] receive fifo full (rfful) 0 = receive fifo is not full 1 = receive fifo is full [10] receive fifo overrun (ovff) 0 = receive fifo is not occured 1 = receive fifo overrun occured [11] receiver in idle (idle) 0 = receiver is in idle state 1 = receiver is in active state c c d o e r t f f u l e _ r x t o t f e m t t h e t c e _ c t s r f f u l r f r e a d c d l i d l e f e r r d v d s r b k d p e r r f e m t o v f f c t s 31 0 3 4 5 1 2 30 29 28 27 26 25 23 22 20 19 15 14 10 9 24 21 18 17 16 13 12 11 8 7 6 figure 10-3. uart status register
S3C4530A uart 10- 13 [12] receive event time out (e_rxto) 0 = a promised time is not elapsed during receiving. 1 = valid data in a promised time (note : a promised time is determined according to wl (word length) : promised time = 4*wl + 12 ) [14] data set ready (dsr) 0 = dsr pin (nudsr) goes high 1 = dsr pin (nudsr) goes low [15] clear to send (cts) 0 = cts pin (nucts) goes high 1 = cts pin (nucts) goes low [16] cts event occured (e_cts) 0 = cts pin (nucts) has changed. 1 = cts pin (nucts) keep it's level [17] transmit complete (tc) 0 = transmit is in progress. 1 = transmit complete ; no data for tx [18] transmit holding register empty (the) 0 = txfifo at trigger level or tranmit holding register is not empty. 1 = in txfifo mode, txfifo at trigger level is empty. in non-fifo mode, transmit holding register is empty. [19] transmit fifo empty (tfemt) 0 = transmit fifo is not empty 1 = transmit fifo is empty [20] transmit fifo full (tfful) 0 = transmit fifo is not full 1 = transmit fifo is full [31:21] reserved c c d o e r t f f u l e _ r x t o t f e m t t h e t c e _ c t s r f f u l r f r e a d c d l i d l e f e r r d v d s r b k d p e r r f e m t o v f f c t s 31 0 3 4 5 1 2 30 29 28 27 26 25 23 22 20 19 15 14 10 9 24 21 18 17 16 13 12 11 8 7 6 figure 10-3. uart status register (continued)
uart S3C4530A 10- 14 table 10-6. ucon0 and ucon1 interrupt enable registers registers offset address r/w description reset value uinten0 0xd008 r/w uart0 interrupt enable register 0x00 uinten1 0xe008 r/w uart1 interrupt enable register 0x00 table 10-7. uart status register description bit number bit name reset value [0] rdvie receive data valid interrupt enable [1] bsdie break signal detected interrupt enable [2] ferie frame error interrupt enable [3] perie parity error interrupt enable [4] oerie overrun error interrupt enable [5] ccdie control character detect interrupt enable [6] dcdlie dcd high at receiver checking time interrupt enable [7] rfreaie receive fifo data trigger level reach interrupt enable [9:8] reserved [10] ovffie receive fifo overrun interrupt enable [11] reserved [12] e_rxtoie receive event time out interrupt enable [15:13] reserved [16] e_ctsie cts event occurred interrupt enable [17] reserved [18] theie transmit holding register empty interrupt enable [31:19] reserved
S3C4530A uart 10- 15 [0] receive data valid interrupt enable (rdrie) [1] break signal detected interrupt enable (bkdie) [2] frame error interrupt enable (ferie) [3] parity error interrupt enable (perie) [4] overrun error interrupt enable (oveie) [5] control character detect interrupt enable (ccdie) [6] data carrier detect lost interrupt enable (dcdlie) [7] receive fifo data trigger level reach interrupt enable (rfreaie) [9:8] reserved [10] receive fifo overrun interrupt enable (ovffie) [11] reserved [12] receive event time out interrupt enable (e_rxtoie) [15:13] reserved [16] cts event occured interrupt enable (e_ctsie) [17] reserved [18] transmit holding register empty interrupt enable (theie) this bit used in fifo mode for interrupt enable when transmit fifo empty as much transmit data trigger level. [31:19] reserved c c d i e o e r i e e _ r x t o i e t h e i e e _ c t s i e r f r e a i e d c d l i e f e r i e r d v i e b k d i e p e r i e o v f f i e 31 0 3 4 5 1 2 30 29 28 27 26 25 23 22 20 19 15 14 10 9 24 21 18 17 16 13 12 11 8 7 6 figure 10-4. uart interrupt enable register
uart S3C4530A 10- 16 uart transmit buffer register S3C4530A has a 32-byte transmit fifo, and the bottom of fifo is utxbuf. all data to be transmitted are stored into this register at first in fifo mode, if next buffer has invalid data, then shifted to next buffer. but in non-fifo mode, a new data to transmit will be moved from utxbuf to tx shift register. the uart transmit buffer registers, utxbuf0 and utxbuf1, contain an 8-bit data value to be transmitted over the uart channel. table 10-8. uxtbuf0 and uxtbuf1 registers registers offset address r/w description reset value utxbuf0 0xd00c w uart0 transmit buffer register 0xxx utxbuf1 0xe00c w uart1 transmit buffer register 0xxx table 10-9. uart status register description bit number bit name reset value [7:0] transmit data this field contains the data to be transmitted over the single channel uart. when this register is written, the transmit buffer register empty bit in the status register, ustat[6], should be "1". this is to prevent overwriting of transmit data that may already be present in the utxbuf. whenever the utxbuf is written with a new value, the transmit register empty bit, ustat[6], is automatically cleared to "0". 31 [7:0] transmit data for uart transmit data 0 7 3 4 6 5 8 1 2 figure 10-5. uart transmit buffer register
S3C4530A uart 10- 17 uart receive buffer register S3C4530A has a 32-byte receive fifo, and the bottom of fifo is urxbuf. all data to be received are stored in this register at first in fifo mode, if next buffer has invalid data, then shifted to next buffer. but in non-fifo mode, a new received data will be moved to urxbuf. the uart receive buffer registers, urxbuf0 and urxbuf1, contain an 8-bit data value to be received over the uart channel. table 10-10. uxrbuf0 and uxrbuf1 registers registers offset address r/w description reset value urxbuf0 0xd010 r uart0 receive buffer register 0xxx urxbuf1 0xe010 r uart1 receive buffer register 0xxx table 10-11. uart transmit register description bit number bit name reset value [7:0] receive data this field contains the data received over the single channel uart. when the uart finishes receiving a data frame, the receive data ready bit in the uart status register, ustat[5], should be "1". this prevents reading invalid receive data that may already be present in the urxbuf. whenever the urxbuf is read, the receive data valid bit(ustat[5]) is automatically cleared to "0". 31 [7:0] receive data for uart receive data 0 7 3 4 6 5 8 1 2 figure 10-6. uart receive buffer register
uart S3C4530A 10- 18 uart baud rate divisor register the values stored in the baud rate divisor registers, ubrdiv0 and ubrdiv1, let you determine the serial tx/ rx clock rate (baud rate) as follows: brgout = (mclk2 or uclk) / (cnt0 + 1) / (16^cnt1) / 16 table 10-12. ubrdiv0 and ubrdiv0 registers registers offset address r/w description reset value ubrdiv0 0xd014 r/w uart0 baud rate divisor register 0x00 ubrdiv1 0xe014 r/w uart1 baud rate divisor register 0x00 31 19 15 16 [3:0] baud reate divisor value cnt1 xxx0 = divide by 1 xxx1 = divide by 16 [15:4] time constant value for cnt0 cnt0 0 18 17 20 30 29 28 27 26 25 24 23 22 21 12 13 14 9 10 11 6 7 8 3 4 5 1 2 cnt1 figure 10-7. uart baud rate divisor register
S3C4530A uart 10- 19 uart baud rate examples uart brg input clock, mclk2 is the system clock frequency divided by 2. if the system clock frequency is 50 mhz and mclk2 is selected, the maximum brgout output clock rate is mclk2/16 (= 1.5625 mhz). uclk is the external clock input pin for uart0, uart1. uart brg input clock, mclk2, uclk can be selected by uccon[6] register. sc mclk2 brgout uclk 12-bit counter divide by 1 or 16 divide by 16 sample clock cnt0 cnt1 note: cnt0 = ubtdivn [15:4], cnt1 = ubrdivn [3:0], sc = ulcon [6] figure 10-8. uart baud rate generator (brg) table 10-13. typical baud rates examples of uart baud rates mclk2 = 25 mhz uclk = 33 mhz (brgout) cnt0 cnt1 freq. dev.(%) cnt0 cnt1 freq. dev.(%) 1200 1301 0 1200.1 0.0 1735 1 1200.08 0.0064 2400 650 0 2400.2 0.0 867 1 2400.15 0.0064 4800 324 0 4807.7 0.2 433 0 4800.31 0.0064 9600 162 0 9585.9 - 0.1 216 0 9600.61 0.0064 19200 80 0 19290.1 0.5 108 0 19113.15 0.45 38400 40 0 38109.8 - 0.8 53 0 38580.15 0.47 57600 26 0 57870.4 0.5 35 0 57870.37 0.47 115200 13 0 111607.1 - 3.1 17 0 115740.74 0.47 230400 6 0 223214.28 3.12 8 0 231481.48 0.47 460860 2 0 520833.34 13.01 4 0 416666.66 9.59
uart S3C4530A 10- 20 uart control character 1 register this control character registers can be used for software flow control. in software flow control mode, you should write control characters into this registers. if not, the reset value will be used as control character. for example, even if you want to use one control character, all control characters will have same value with it. table 10-14. ucc1 _0 and ucc1_1 registers registers offset address r/w description reset value conchar1_0 0xd018 r/w uart0 control character 1 register 0x00 conchar1_1 0xe018 r/w uart1 control character 1 register 0x00 31 19 15 16 [7:0] control character 0 [15:8] control character 1 [23:16] control character 2 [31:24] control character 3 conchar0 0 18 17 20 30 29 28 27 26 25 24 23 22 21 12 13 14 9 10 11 6 7 8 3 4 5 1 2 conchar1 conchar3 conchar2 figure 10-9. uart control character 1 register
S3C4530A uart 10- 21 uart control character 2 register this control character registers can be used for software flow control. in software flow control mode, you should write control characters into this registers. if not, the reset value will be used as control character. for example, even if you want to use one control character, all control characters will have same value with it. table 10-15. ucc2_0 and ucc2_1 registers registers offset address r/w description reset value ucc2_0 0xd01c r/w uart0 control character 2 register 0x00 ucc2_1 0xe01c r/w uart1 control character 2 register 0x00 31 19 15 16 [7:0] control character 4 [15:8] control character 5 [23:16] control character 6 [31:24] control character 7 conchar4 0 18 17 20 30 29 28 27 26 25 24 23 22 21 12 13 14 9 10 11 6 7 8 3 4 5 1 2 conchar5 conchar7 conchar6 figure 10-10. uart control character 2 register
uart S3C4530A 10- 22 < receiver > < transmitter > urxbuf int_rxd urxdn previous receive data parity data bits (5-8) stop (1-2) start start data bits valid receive data wr_thr int_txd thre utxdn parity start data bits (5-8) stop (1-2) start figure 10-11. interrupt-based serial i/o timing diagram ( tx and rx only)
S3C4530A uart 10- 23 wr_thr nxdreq thre txd txe select dma mode nxdack parity start data bits (5-8) stop (1-2) figure 10-12. dma-based serial i/o timing diagram ( tx only) < receiver > urxbufn nxdreq urxdn previous receive data parity data bits (5-8) stop (1-2) start start data bits valid receive data txe select dma mode nxdack figure 10-13. dma-based serial i/o timing diagram (rx only)
uart S3C4530A 10- 24 0 1 0 1 0 0 1 1 0 1 start bit stop bit data bits sio frame figure 10-14. serial i/o frame timing diagram (normal uart) 0 1 0 1 0 0 1 1 0 1 start bit stop bit data bits ir transmit frame bit frame = t 3/16t 7/16t 6/16t figure 10-15. infra-red transmit mode frame timing diagram
S3C4530A uart 10- 25 0 1 0 1 0 0 1 1 0 1 start bit stop bit data bits ir transmit frame bit frame = t 3/16t 13/16t figure 10-16. infra-red receive mode frame timing diagram
uart S3C4530A 10- 26 [note] you can refer the application note of ks32c50100 on using the uart, the general items related on it will not be covered in this manual . programming guide for using autobaudrate the S3C4530A has the auto-baud rate block which detects the channel speed and sets the uartbrd registers. (see figure 10-19). but the start bit duration is variable in the real line, so you need to change the uartbrd register value into the nearest corresponding baud-rate value by software. to detect auto-baud rate, the abrd bit in the uartcon should be set before receiving any uart rx data. before the position (1) in fig 10-19, you should set the abrd bit. after doing this, if the uart rx data coming, the uart block will detect the start bit and calculate the duration until it meet the rising edge of urxd. that ?s why you should set the lsb of the urxd as ?1?. after finishing the calculation, the abrd bit will be cleared automatically at the position (2) in fig 10-19and the uart write the uartbrd register as the calculated value at the same time. but you can meet the frame error or parity error, because this value is not exact one in the real line, you can see the start bit is shorter than the ideal one, see the figure 10-19 urxd start stop data parity urxd start stop data parity (1) (2) (3) (b) real uart rx data (uneven spacing) (a) ideal uart rx data (even spacing) figure 10-17. uart rx data (ideal one and real one)
S3C4530A uart 10- 27 pre-requisition for using auto baud rate first of all, if the line speed is higher than 57600 bps and you use the setting value of uartbrd without s/w reconfiguration, the first character can be error. setting the nearest baud rate is our design goal. but some application requires even the received first character without any error within the tolerant error rate. to do this, you need to follow the pre-requisition. however, even you followed this method, it is impossible to support the higher speed than 460k. the highest speed for auto-baud rate is the 230k bps when using the external 29.4912mhz clock. 1) using the external 29.4912mhz uart clock. 2) connect the uart rxd line to one of the xintreq[x]. 3) using the fiq for the servicing xintreq[x] , this is only one fiq, you cannot use any other fiq. 4) implement the uart reconfiguration which is recommended in listing 2. auto baud rate initialization to use the auto baud rate, you need to prepare the following initialize codes. listing 1. auto baud rate initializing code void autobaudrateinitial(void) { uartcon1 |= abrd ; iopcon = (0x16 << 5*extint #n ) ; intmode = 0x1 << ( extint #n); iopmod = 0x3ffff; uartbrd1 = 0x0; // this is used to reconfigure see the listing 2 intpend = 0x1 << ( extint #n); enable_int( next#n_int); } after executing the above code, the uart is ready to receive the first character and set the uartbrd value. because the urxd pin is connected to the xintreq , when the rxd is coming , the fiq interrupt will be generated. but in this case, you bear in mind that if urxd is transited before starting, xintreq pending bit can be set. so before enabling the external interrupt, you should clear the interrupt pending bit.
uart S3C4530A 10- 28 handling the fiq intrrupt even you use the fiq mode, it takes few micro-seconds to meet the reconfiguration s/w. the faster reconfiguration, you get the better result. for this reason, we provide the following the assembly service routine. so you should design your low-level driver based on this code. listing 2. fiq handler for speeding up the uartbrd reconfiguration ; this is the limit value for the external uart clock 29.912 mhz ; if you use internal clock or the other external uart clock you should modify this values baud230klimit equ 0xa0 ; brd ( 0x0~0xa0 =>0x70) baud115klimit equ 0x180 ; brd ( 0xa0~0x180 =>0xf0) baud56klimit equ 0x280 ; brd ( 0x180~0x280 =>0x1f0) baudval230k equ 0x70 ; brd ( 0x0~0xa0 =>0x70) baudval115k equ 0xf0 ; brd ( 0xa0~0x180 =>0xf0) baudval56k equ 0x1f0 ; brd ( 0x180~0x280 =>0x1f0) systemfiqhandler abdloop mov r9,#0x4000000 sub r9,r9,#0x2000 ; if you use the uart channel a, you need to ; change the 0x2000 to 0x3000 ldr r9,[r9,#0x14] mov r10,r9 cmp r9,#0x0 bne abdset b abdloop abdset reconfig ldr r11,=baud230klimit cmp r10,r11 bgt baud115k ldr r9,= baudval230k mov r10,#0x4000000 sub r10,r10,#0x2000 str r9,[r10,#0x14] b start_uart_rx baud115k ldr r11,= baud115klimit cmp r10,r11 bgt baud56k ldr r9,= baudval115k mov r10,#0x4000000 sub r10,r10,#0x2000 str r9,[r10,#0x14]
S3C4530A uart 10- 29 b start_uart_rx baud56k ldr r11,= baud56klimit cmp r10,r11 bgt start_uart_rx ldr r9,= baudval56k mov r10,#0x4000000 sub r10,r10,#0x2000 str r9,[r10,#0x14] b start_uart_rx start_uart_rx stmfd sp!, { lr} bl startuartreceive ldmfd sp!, { lr} subs pc, lr, #4 if the fiq interrupt generated, wait until the uartbrd value is set by h/w. that ?s why we initialize the uartbrd value as ?0?. this scheme will reduce the instructions to check abrd bit and read uartbrd register. comparing the uartbrd with ?0?, if h/w write the uartbrd, then start to reconfigure by s/w. we use the simple way to reconfigure the uartbrd. firstly check the uart230klimit, because it is impossible to support the 460k speed. and finishing the reconfigure after 56k detection, because you can always get the correct data with the uartbrd by h/w with the speed slower than 56k. you can see the general registers are not dumped into stack. we use only the banked register of fiq mode, so the shared registers from r0~r7 is not moved. this is a different point from the ordinary fiq service routine. and this fiq service routine is only for uart baud reconfiguration. this means you cannot use any other fiq interrupt. listing 3. startuartreceive funciton void startuartreceive(void) { uartrxinton(1); intpend = 0x1 << ( extint #n); disable_int( next#n_int); } this function will set the uart rx interrupt on to handle the received uart data. the important thing is the s/w reconfiguration is used once for the start bit of first character. so disable the xintreq interrupt.
uart S3C4530A 10- 30 programming guide for using uart tx/rx fifo and flow control in S3C4530A, some functions are appended with s3c4510b device for the high-speed uart. the 32-byte tx and rx fifo are inside, which lessen the cpu load as well as data loss. also adding the modem h/w interface signals, which give the merit that no modification is used for rts and cts anymore. s/w flow control gives the flexible serial data controls. the following descriptions are only for the different feature of S3C4530A from s3c4510b. refer the application note of ks32c50100 on using the uart for basic functions. uart initialize for S3C4530A the uart should be initialized before getting into operation. uartinitialize(), and uartportinit() function is used for this initialization. in the following, describe the contents of this function. in the high-speed operation of uart, you can select the tx/rx fifo enable. also if enabling the software flow control and hardware flow control, it makes easy to implement the modem interface. when setting up uart controller, we use tuartdev structure, this has all parameter that should be setup for normal operation. the device_entry structure is described in listing 4 listing 4. tuartdev structure for S3C4530A (uart.h) // definition for uart device typedef struct { u32 port ; // uart port number u32 srcclk ; // tx/rx clock pin output source. u32 baudrate ; // uart baudrate u32 parity ; // uart data format u32 wordlength ; u32 stopbit ; u32 autobauden; u32 txfifo; u32 rxfifo; u32 hwflow; u32 swflow; } tuartdev ; the initial value for each hdlc controller is described in source code listing 5 . after initializing the hdlc parameter, the hdlcportinit() function is used for initialize each port with initialization parameter value
S3C4530A uart 10- 31 listing 5. uartinitialize( ) function (uartinit.c) // uart device tuartdev uartdev[num_of_uart_port] = { { uart0, // port uclk, // clock selection uart_baudrate, // uart baud rate parity_no, // num of parity bit wl8, // word length stb1, // stop bit; abrddis, // auto-baud rate control tfen, // txfifo enable rfen, // rxfifo enable hwfcdis, // hardware flow contol enable swfcdis, // software flow contol enable & guartrxstatus[uart0] },{ ? } } /* * function : uartinitialize * description : uart controller initialize */ void uartinitialize(void) { int channel; tuartdev * uart; // step 1. global interrupt disable during uart initializing. disable_int( nglobal_int); // step 2. initialize each uart port for(channel=uart0 ; channel<=uart1 ; channel++) { uart = ( tuartdev *)& uartdev[channel]; if ( ! uartportinit( uart) ) print("\n uart channel [%d] initialize error",channel) ; /* interrupt service routine setup */ syssetuartinterrupt(channel) } // step 3. enable interrupt enable_int( nglobal_int); } after setup uart parameter, the main uart initialization is performed by uartportinit() function. the detail of uart initialization function is described in source code listing 6-
uart S3C4530A 10- 32 listing 6. uartportinit() function (uartinit.c) /* * function : uartportinit * description : uart port initialize */ int uartportinit( tuartdev * uart) { u32 channel = uart->port ; /* initialize uart transmi t & receive queue */ txqueinit(channel); rxqueinit(channel); /* uart interrupt off */ uartrxintoff(channel); uarttxintoff(channel); /* default baud rate will be set. sysconf.h */ uartbrd(channel) = getuartbaudrate( extuclk,uart->baudrate); uartcon(channel) = uart->wordlength |\ uart->parity |\ uart->stopbit ; // check the source clock checkandenableuartclk; // check the fifo mode and enable checkandenablefifomode; // check the flow contol and enable checkandenableflowcontrol; // if autobaudrate, start autobaudrate. checkandstartautobaudrate; uartcon(channel) |= rxmode_int | txmode_int ; return 1; } // definnition for uart configuration #define checkandenableuartclk \ if( uart->srcclk) uartcon(channel) |= uclk ; #define checkandenablefifomode \ if( uart->txfifo) uartcon(channel) |= txtl16 | tfen ;\ if( uart->rxfifo) uartcon(channel) |= rxtl28 | rfen ; #define checkandenableflowcontrol \ if( uart->hwflow)\ {\
S3C4530A uart 10- 33 uartcon(channel) |= hfen | dtr_low;\ iopcon |= uartdcd(channel) | uartcts(channel) | uartrts(channel) | \ uartrxd(channel) | uartdsr(channel) | uarttxd(channel) | uartdtr(channel) ;\ }\ if( uart->swflow)\ {\ uartchar1(channel) = (xon1<<24) | (xon1<<16) | (xoff3<<8) | xoff3 ;\ uartchar2(channel) = (xon3<<24) | (xon3<<16) | (xoff1<<8) | xoff1 ;\ uartcon(channel) |= sfen ;\ } #define checkandstartautobaudrate \ if( uart->autobauden) setautobaud(channel); according to the uartdev structure member value, uartportinit function will initialize each uart port. and the definitions show special settings for adequate operation in listing 6. uart polled i/o functions the get_char() is implemented for to receive data through uart channel in polling method. if the uart receive buffer register[ urxbufn] is filled with received data, then rdv bit of uart status will be set, and the get_char() will return the byte data of uexbufn. in this case, if the oer,fer and per errors happen, this bit should be cleared before receving next serial data, listing 7. poll i/o functions (uartlib.c,uart.h) #define waitrcver(channel) \ while(!(uartstat(channel) & rdv)) uartstat(channel) = oer | fer | per; char get_char(uint32 channel) { waitrcver(channel); return uartrxb(channel); } uart functions for interrupt the uart interrupt service routines for data transferring are already registered at interrupt vector table at uart initialize function, uartinitialize(), is called. (listing 5). S3C4530A has the uartinten register, which is mainly different from s3c4510b. so the uart tx/rx interrupt mask bit is used for handling the interrupt enable and disble in case of s3c4510b. but uartinten register bits are used for S3C4530A. you can see it in lising. 8.
uart S3C4530A 10- 34 listing 8. (uartinit.c) /*****************************/ /* interrupt servive routine */ /*****************************/ void uarttxinton(uint32 channel) { u32 uart_tx_int ; uart_tx_int = (channel)? nuart1_tx_int : nuart0_tx_int ; uartinten(channel) |= th_emptyie; enable_int( uart_tx_int); } void uartrxinton(uint32 channel) { u32 uart_rx_int ; uart_rx_int = (channel)? nuart1_rx_err_int : nuart0_rx_err_int ; /* enable interrupt */ if(uartcon(channel) & rfen){ uartinten(channel) &= ~rdvie ; uartinten(channel) = rf_tlie | rx_e_toie ; } else { uartinten(channel) = rdvie | bsdie | ferie | perie | oerie |\ ccdie | rf_tlie | rf_overie | rx_e_toie ; } enable_int( uart_rx_int); } void uarttxintoff(uint32 channel) { u32 uart_tx_int ; uart_tx_int = (channel)? nuart1_tx_int : nuart0_tx_int ; uartinten(channel) &= ~th_emptyie; enable_int( uart_tx_int); } void uartrxintoff(uint32 channel) { u32 uart_rx_int ; uart_rx_int = (channel)? nuart1_rx_err_int : nuart0_rx_err_int ; disable_int( uart_rx_int); }
S3C4530A uart 10- 35 uart functions for interrupt service routine in non-fifo mode, it is easy to handle the interrupt service. if the tx interrupt happen, it should be th_empty interrupt. by writing the data into uarttxh(holding register) , you can send data through uart tx line. as the same way, if the rx interrupt happen, just check whether the data is received well or not. (rdv,fer,per,oer) and then process the next procedure for each case. in fifo mode, the service routine is somewhat complicated. if the tx interrupt happen, that means transmit fifo is empty to trigger level. so we need to write the data at the extent to the tx buffer size. when buffering the tx data, you need to monitor whether the tranmit fifo full or not. interrupt service routine meets the null data or fifo full, then exit the interrupt service routine. if the rx interrupt happen, the buffered data has their own receive status. therefore, until the rxfifo empty monitored, read the status and data and process corresponding procedure. also if it meet the rxfifo full , give the send break to the peer count. listing 9. (uartisr.c) void uarttxisr(uint32 channel) { u32 txstatus ; txstatus = uartstat(channel) ; if ( txstatus & ( th_empty | tf_empty) ) uarttxh(channel)= txqueread(channel); else uarttxintoff(channel); } void uarttxfifoisr(uint32 channel) { u32 txstatus ; u32 i ; u32 depth; u32 data; txstatus = uartstat(channel) ; if ( txstatus & ( th_empty | tf_empty)) { depth = gettxfifosize(channel); for(i=0 ; i uart S3C4530A 10- 36 u32 intuartstatus ; turxstatus * rxstatus; intuartstatus = uartstat(channel) ; if ( intuartstatus & rdv){ rxquewrite(uartrxb(channel),channel) ; } else { chk_clr_ustat(bsd); chk_clr_ustat(fer); chk_clr_ustat(per); chk_clr_ustat(oer); chk_clr_ustat(ccd); # ifdef debug_uart update_uart_rx_status(op_mode_cpu) # endif } } void uartrxfifoerrisr(uint32 channel) { u32 intuartstatus ; uint32 depth; u32 i ; turxstatus * rxstatus; depth = getrxfifosize(channel); for(i=0;i S3C4530A uart 10- 37 } } chk_clr_ustat( rf_over); chk_clr_ustat( rx_e_to); } listing 10. (uartinit.c) uint32 gettxfifosize(uint32 channel) { uint32 index; switch((uartcon(channel) & txtlm)) { case txtl30 : index = 30; break; case txtl24 : index = 24; break; case txtl16 : index = 16; break; case txtl8 : index = 8; break; } return(index); } uint32 getrxfifosize(uint32 channel) { uint32 index; switch((uartcon(channel) & rxtlm)) { case rxtl1 : index = 1; break; case rxtl8 : index = 8; break; case rxtl18 : index = 18; break; case rxtl28 : index = 28; break; } return(index); }
uart S3C4530A 10- 38 notes
S3C4530A 32-bit tim ers 11- 1 11 32-bit timers overview the S3C4530A has two 32-bit timers. these timers can operate in interval mode or in toggle mode. the output signals are tout0 and tout1, respectively. you enable or disable the timers by setting control bits in the timer control register, tcon. an interrupt request is generated whenever a timer count-out (down count) occurs. interval mode operation in interval mode, a timer generates a one-shot pulse of a preset timer clock duration whenever a time-out occurs. this pulse generates a time-out interrupt that is directly output at the timer's configured output pin ( toutn). in this case, the timer frequency monitored at the toutn pin is calculated as: f tout = f mclk / timer data value toggle mode operation in toggle mode, the timer pulse continues to toggle whenever a time-out occurs. an interrupt request is generated whenever the level of the timer output signal is inverted (that is, when the level toggles). the toggle pulse is output directly at the configured output pin. using toggle mode, you can achieve a flexible timer clock range with 50% duty. in toggle mode, the timer frequency monitored at the toutn pin is calculated as follows: f tout = f mclk / (2 * timer data value) f tout f tout time-out time-out time-out interval mode toggle mode (initial toutn is 0) figure 11-1. timer output signal timing
32-bit timers s3c45 30a 11- 2 timer operation guidelines the block diagram in figure 11-2 shows how the 32-bit timers are configured in the S3C4530A. the following guidelines apply to timer functions. ? when a timer is enabled, it loads a data value to its count register and begins decrement the count register value. ? when the timer interval expires, the associated interrupt is generated. the base value is then reloaded and the timer continues decrement its count register value. ? if a timer is disabled, you can write a ne w base value into its registers. ? if the timer is halted while it is running, the base value is not automatically re-loaded. f mclk 32-bit timer count register (tcntn) [down counter] 32-bit timer data register (tdatan) pulse generator tmod.ten tmod.tmdn tmod.tclrn pnd intpnd and intmsk interrupt request port 16, port 17 data out iopcon.toenn auto re-load toutn figure 11-2. 32-bit timer block diagram
S3C4530A 32-bit tim ers 11- 3 timer mode register the timer mode register, tmod, is used to control the operation of the two 32-bit timers. tmod register settings are described in figure 11-3. table 11-1. tmod register register offset address r/w description reset value tmod 0x6000 r/w timer mode register 32 ?h 00000000 [0] timer 0 enable (te0) 0 = disable timer 0 1 = enable timer 0 [1] timer 0 mode selection (tmd0) 0 = interval mode 1 = toggle mode [2] timer 0 initial tout0 value (tclr0) 0 = initial tout0 is 0 in toggle mode 1 = initial tout0 is 1 in toggle mode [3] timer 1 enable (te1) 0 = disable timer 1 1 = enable timer 1 [4] timer 1 mode selection (tmd1) 0 = interval mode 1 = toggle mode [5] timer 1 initial tout1 value (tclr1) 0 = initial tout1 is 0 in toggle mode 1 = initial tout1 is 1 in toggle mode 31 0 6 3 4 5 1 2 t d m 0 t e 1 t e 0 t d m 1 t c l r 1 t c l r 0 figure 11-3. timer mode register (tmod)
32-bit timers s3c45 30a 11- 4 timer data registers the timer data registers, tdata0 and tdata1, contain a value that specifies the time-out duration for each timer. the formula for calculating the time-out duration is: (timer data + 1) cycles. table 11-2. tdata0 and tdata1 registers register offset address r/w description reset value tdata0 0x6004 r/w timer 0 data register 0x00000000 tdata1 0x6008 r/w timer 1 data register 0x00000000 31 [31:0] timer 0/1 data value receive data 0 figure 11-4. timer data registers (tdata0, tdata1) timer count registers the timer count registers, tcnt0 and tcnt1, contain the current timer 0 and 1 count value, respectively, during normal operation. table 11-3. tcnt0 and tcnt1 registers register offset address r/w description reset value tcnt0 0x600c r/w timer 0 counter register 0xffffffff tnct1 0x6010 r/w timer 1 counter register 0xffffffff 31 [31:0] timer 0/1 count value timer count 0 figure 11-5. timer counter registers (tcnt0, tcnt1)
S3C4530A i/o por ts 12- 1 12 i/o ports overview the S3C4530A has 26 programmable i/o ports. you can configure each i/o port to input mode, output mode, or special function mode. to do this, you write the appropriate settings to the iopmod and iopcon0/1 registers. user can set filtering for the input ports using iopcon0/1 registers. the port0 and port1 can be determined by the iopmod register. but port[11:8] can be used as xintreq[3:0], port[13:12] as nxdreq[1:0], port[15:14] as nxdack[1:0], port[16] as tout0, port[17] as tout1 depending on the settings in iopcon0 register. the port[7:2] and port[25:18] can be operated uart signal by iopcon1 register. the port[7:2] default function is general i/o port and port[25:18] default function is uart port. these ports can be controlled by iopcon1 register. system bus output latch input latch active on/off & edge detection iopdata (read) interrupt or dma request iopcon filter on/off iopcon iopdata (write) alternate functions iopcon v dd iopmod port11/xintreq3 port12/nxdreq0 port13/nxdreq1 port14/nxdack0 port15/nxdack1 port16/tout0 port17/tout1 port25/dtr1 port0 - port1 port2/dcd0 port3/cts0 figure 12-1. i/o port function diagram
i/o ports s3c4530x risc microcontroller 12- 2 i/o port special registers four registers control the i/o port configuration: iopmod, iopcon0/1, and iopdata. these registers are described in detail below. i/o port mode register (iopmod) the i/o port mode register, iopmod, is used to configure the port pins, p25-p0. note if the port is used for a special function such as an external interrupt request, an external dma request, or acknowledge signal or timer outputs or uart signal, its mode is determined by the iopcon0/1 register, not by iopmod. table 12-1. iopmod register register offset address r/w description reset value iopmod 0x5000 r/w i/o port mode register 0x00000000 31 15 16 [0] i/o port mode bit for port 0 0 = input 1 = output [1] i/o port mode bit for port 1 0 = input 1 = output [2] i/o port mode bit for port 2 0 = input 1 = output [25] i/o port mode bit for port 17 0 = input 1 = output x 0 18 17 12 13 14 9 10 11 6 7 8 3 4 5 1 2 x x x x x x x x x x x x x x x x x 24 25 x 21 22 23 19 20 x x x x x x x figure 12-2. i/o port mode register (iopmod)
S3C4530A i/o por ts 12- 3 i/o port control register (iopcon) the i/o port control register, iopcon, is used to configure the port pins, p17-p8. note if the port is used for a special function such as an external interrupt request, an external dma request, or acknowledge signal and timer outputs, its mode is determined by the iopcon register, not by iopmod. for the special input ports, S3C4530A provides 3-tap filtering. if the input signal levels are same for the three system clock periods, that level is taken as input for dedicated signals such as external interrupt requests and external dma requests. table 12-2. iopcon register register offset address r/w description reset value iopcon0 0x5004 r/w i/o port control register 0x00000000
i/o ports s3c4530x risc microcontroller 12- 4 [4:0] control external interrupt request 0 input for port 8 (xirq0) [4] port 8 for xintreq0 0 = disable 1 = enable [3] 0 = active low 1 = active high [2] 0 = filtering off 1 = filtering on [1:0] 00 = level detection 01 = rising edge detection 10 = falling edge detection 11 = both edge detection [9:5] control edternal interruot request 1 input for port 9 (xirq1) (see control external interrupt request 1.) [14:10] control external interrupt request 2 input for port 10 (xirq2) (see control external interrupt request 2.) [19:15] control external interrupt request 3 input for port 10 (xirq3) (see control external interrupt request 3.) [22:20] control external dma request 0 input for port 12 (drq0) [22] port 12 for nxdreq0 0 = disable 1 = enable [21] 0 = filtering off 1 = filtering on [20] 0 = active low 1 = active high [25:23] control external dma request 1 input for port 13 (drq1) [25] port 13 for nxdreq1 0 = disable 1 = enable [24] 0 = filtering off 1 = filtering on [23] 0 = active low 1 = active high [27:26] control external dma acknowledge 0 output for port 14 (dak0) [27] port 14 for nxdack0 0 = disable 1 = enable [26] 0 = active low 1 = active high [29:28] control external dma acknowledge 1 output for port 15 (dak1) [29] port 15 for nxdack1 0 = disable 1 = enable [28] 0 = active low 1 = active high [30] control timeout 0 for port 16 (toen0) 0 = disable 1 = enable [31] control timeout 1 for port 17 (toen1) 0 = disable 1 = enable 31 0 3 4 5 1 2 d a k 1 t o e n 1 30 29 28 27 26 25 23 22 20 19 15 14 10 9 t o e n 0 d a k 0 d r q 1 d r q 0 x i r q 3 x i r q 2 x i r q 1 x i r q 1 figure 12-3. i/o port control register 0 (iopcon0)
S3C4530A i/o por ts 12- 5 i/o port data register (iopdata) the i/o port data register, iopdata, contains one-bit read values for i/o ports that are configured to input mode and one-bit write values for ports that are configured to output mode. bits[25:0] of the 26-bit i/o port register value correspond directly to the 26 port pins, p25-p0. table 12-3. iopdata register register offset address r/w description reset value iopdata 0x5008 r/w i/o port data register undefined [25:0] i/o port read/write values for ports 25 - 0 (p25 - p0) note: the values in the i/o port data register reflect the signal level on the respective i/o port pins. when the ports are configured to output mode, the bit reflects the ports write value. when the port is configured to input mode, the bit reflects the ports read value. 31 9 8 7 6 5 4 3 2 1 0 p 1 p 0 p 10 p 9 p 8 p 7 p 6 p 5 p 4 p 3 p 2 18 17 16 15 14 13 12 11 10 p 17 p 16 p 15 p 14 p 13 p 12 p 11 25 24 23 22 21 20 19 p 23 p 22 p 21 p 20 p 19 p 18 p 24 p 25 figure 12-4. i/o port data register (iopdata)
i/o ports s3c4530x risc microcontroller 12- 6 i/o port control register (iopcon1) the i/o port control register 1, iopcon1, is used to configure the port pins, p7-p2 and p25-p18. you can configure uart modem interface signals or i/o port by this register set. note if the port is used for a uart function, its mode can be determined by the iopcon1 register. this register default value, p7-p2 is zero, that is i/o port function and p25-p18 is one that is uart function. table 12-4. iopcon1 register register offset address r/w description reset value iopcon1 0x500c r/w i/o port data register 0x03fc0000
S3C4530A i/o por ts 12- 7 31 [1:0] reserved [2] uart dcd0 or port2 0 = port 2 1 = dcd0 [3] uart cts0 or port3 0 = port 3 1 = cts0 [4] uart rts0 or port4 0 = port 4 1 = rts0 [5] uart dcd1 or port5 0 = port 5 1 = dcd1 [6] uart cts1 or port6 0 = port 6 1 = cts1 [7] uart rts1 or port7 0 = port 7 1 = rts1 [17:8] reserved x x x x x x 22 23 25 24 19 20 21 15 16 0 18 17 12 13 14 9 10 11 6 7 8 3 4 5 1 2 x x x x x x x x [18] port18 or uart rxd0 0 = port 18 1 = rxd0 [19] port19 or uart dsr0 0 = port 19 1 = dsr0 [20] port20 or uart txd0 0 = port 20 1 = txd0 [21] port21 or uart dtr0 0 = port 21 1 = dtr0 [22] port22 or uart rxd1 0 = port 22 1 = rxd1 [23] port23 or uart dsr1 0 = port 23 1 = dsr1 [24] port24 or uart txd1 0 = port 24 1 = txd1 [25] port25 or uart dtr1 0 = port 25 1 = dtr1 figure 12-5. i/o port control register 1 (iopcon1)
i/o ports s3c4530x risc microcontroller 12- 8 iopcon.xirqn [1:0] (= 00) iopcon.xirqn [1:0] (= 01) internal intreqn xintreqn mclk iopcon.xirqn [1:0] (= 10) iopcon.xirqn [1:0] (= 11) figure 12-6. external interrupt request timing (active high) iopcon.xirqn [1:0] (= 00) iopcon.xirqn [1:0] (= 01) internal intreqn xintreqn mclk iopcon.xirqn [1:0] (= 10) iopcon.xirqn [1:0] (= 11) figure 12-7. external interrupt request timing (active low)
S3C4530A interrupt controller 13- 1 13 interrupt controlle r overview the S3C4530A interrupt controller has a total of 21 interrupt sources. interrupt requests can be generated by internal function blocks and at external pins. the arm7tdmi core recognizes two kinds of interrupts: a normal interrupt request (irq), and a fast interrupt request (fiq). therefore all S3C4530A interrupts can be categorized as either irq or fiq. the S3C4530A interrupt controller has an interrupt pending bit for each interrupt source. four special registers are used to control interrupt generation and handling: ? interrupt priority registers. the index number of each interrupt source is written to the pre-defined interrupt priority register field to obtain that priority. the interrupt priorities are pre-defined from 0 to 20. ? interrupt mode register. defines the interrupt mode, irq or fiq, for each interrupt source. ? interrupt pending register. indicates that an interrupt request is pending. if the pending bit is set, the interrupt pending status is maintained until the cpu clears it by writing a "1" to the appropriate pending register. when the pending bit is set, the interrupt service routine starts whenever the interrupt mask register is "0". the service routine must clear the pending condition by writing a "1" to the appropriate pending bit. this avoids the possibility of continuous interrupt requests from the same interrupt pending bit. ? - - interrupt mask register. indicates that the current interrupt has been disabled if the corresponding mask bit is "1". if an interrupt mask bit is "0" the interrupt will be serviced normally. if the global mask bit (bit 21) is set to "1", no interrupts are serviced. however, the source's pending bit is set if the interrupt is generated. when the global mask bit has been set to "0", the interrupt is serviced.
interrupt controller S3C4530A 13- 2 interrupt sources the 21 interrupt sources in the S3C4530A interrupt structure are listed, in brief, as follows: table 13-1. S3C4530A interrupt sources index values interrupt sources [20] i 2 c-bus interrupt [19] ethernet controller mac rx interrupt [18] ethernet controller mac tx interrupt [17] ethernet controller bdma rx interrupt [16] ethernet controller bdma tx interrupt [15] hdlc channel b rx interrupt [14] hdlc channel b tx interrupt [13] hdlc channel a rx interrupt [12] hdlc channel a tx interrupt [11] timer 1 interrupt [10] timer 0 interrupt [9] gdma channel 1 interrupt [8] gdma channel 0 interrupt [7] uart 1 receive and error interrupt [6] uart 1 transmit interrupt [5] uart 0 receive and error interrupt [4] uart 0 transmit interrupt [3] external interrupt 3 [2] external interrupt 2 [1] external interrupt 1 [0] external interrupt 0
S3C4530A interrupt controller 13- 3 interrupt controller special registers interrupt mode register bit settings in the interrupt mode register, intmod, specify if an interrupt is to be serviced as a fast interrupt (fiq) or a normal interrupt (irq). table 13-2. intmod register register offset address r/w description reset value intmod 0x4000 r/w interrupt mode register 0x00000000 31 15 16 [20:0] interrupt mode bits note : each of the 21 bits in the interrupt mode enable register, intmod, corresponds to an interrupt source. when the source interrupt mode bit is set to 1, the interrupt is processed by the arm7tdmi core in fiq (fast interrupt) mode. otherwise, it is processed in irq mode (normal interrupt). the 21 interrupt sources are mapped as follows: [20] i2c interrupt [19] ethernet controller mac rx interrupt [18] ethernet controller mac tx interrupt [17] ethernet controller bdma rx interrupt [16] ethernet controller bdma tx interrupt [15] hdlc channel b rx interrupt [14] hdlc channel b tx interrupt [13] hdlc channel a rx interrupt [12] hdlc channel a tx interrupt [11] timer 1 interrupt [10] timer 0 interrupt [9] gdma channel 1 interrupt [8] gdma channel 0 interrupt [7] uart1 receive and error interrupt [6] uart1 transmit interrupt [5] uart0 receive and error interrupt [4] uart0 transmit interrupt [3] external interrupt 3 [2] external interrupt 2 [1] external interrupt 1 [0] external interrupt 0 x 0 18 17 12 13 14 9 10 11 6 7 8 3 4 5 1 2 x x x x x x x x x x x x x x x x x 19 21 20 x x x intmod figure 13-1. interrupt mode register (intmod)
interrupt controller S3C4530A 13- 4 interrupt pending register the interrupt pending register, intpnd, contains interrupt pending bits for each interrupt source. this register has to be cleared at the top of an interrupt service routine. table 13-3. intpnd register register offset address r/w description reset value intpnd 0x4004 r/w interrupt pending register 0x00000000 31 15 16 [20:0] interrupt pending bits note : each of the 21 bits in the interrupt mode pending register, intpnd, corresponds to an interrupt source. when an interrupt request is generated, its pending bit is set to 1. the service routine must then clear the pending condition by writing a 1 to the apropriate pending bit at start. the 21 interrupt sources are mapped as follows: [20] i2c interrupt [19] ethernet controller mac rx interrupt [18] ethernet controller mac tx interrupt [17] ethernet controller bdma rx interrupt [16] ethernet controller bdma tx interrupt [15] hdlc channel b rx interrupt [14] hdlc channel b tx interrupt [13] hdlc channel a rx interrupt [12] hdlc channel a tx interrupt [11] timer 1 interrupt [10] timer 0 interrupt [9] gdma channel 1 interrupt [8] gdma channel 0 interrupt [7] uart1 receive and error interrupt [6] uart1 transmit interrupt [5] uart0 receive and error interrupt [4] uart0 transmit interrupt [3] external interrupt 3 [2] external interrupt 2 [1] external interrupt 1 [0] external interrupt 0 x 0 18 17 12 13 14 9 10 11 6 7 8 3 4 5 1 2 x x x x x x x x x x x x x x x x x 19 21 20 x x x intpnd figure 13-2. interrupt pending register (intpnd)
S3C4530A interrupt controller 13- 5 interrupt mask register the interrupt mask register, intmsk, contains interrupt mask bits for each interrupt source. table 13-4. intmsk register register offset address r/w description reset value intmsk 0x4008 r/w interrupt mask register 0x003fffff 31 15 16 [20:0] individual interrupt mask bits note: each of the 21 bits in the interrupt mask register, intmsk, (except for the global mask bit, g) corresponds to an interrupt source. when a source interrupt mask bit is 1, the interrupt is not serviced by the cpu when the corresponding interrupt request is generated. if the mask bit is 0, the interrupt is serviced upon request. and if global mask bit (bit 21) is 1, no interrupts are serviced. (however, the source pending bit is set whenever the interrupt is generated.) after the global mask bit is cleared, the interrupt is serviced. the 21 interrupt sources are mapped as follows: [20] i2c interrupt [19] ethernet controller mac rx interrupt [18] ethernet controller mac tx interrupt [17] ethernet controller bdma rx interrupt [16] ethernet controller bdma tx interrupt [15] hdlc channel b rx interrupt [14] hdlc channel b tx interrupt [13] hdlc channel a rx interrupt [12] hdlc channel a tx interrupt [11] timer 1 interrupt [10] timer 0 interrupt [9] gdma channel 1 interrupt [8] gdma channel 0 interrupt [7] uart1 receive and error interrupt [6] uart1 transmit interrupt [5] uart0 receive and error interrupt [4] uart0 transmit interrupt [3] external interrupt 3 [2] external interrupt 2 [1] external interrupt 1 [0] external interrupt 0 [21] global interrupt mask bit 0 = enable interrupt requests 1 = disable all interrupt requests x 0 18 17 12 13 14 9 10 11 6 7 8 3 4 5 1 2 x x x x x x x x x x x x x x x x x 19 21 20 x x g intmsk figure 13-3. interrupt mask register (intmsk)
interrupt controller S3C4530A 13- 6 interrupt priority registers the interrupt priority registers, intpri0?intpri5, contain information about which interrupt source is assigned to the pre-defined interrupt priority field. each intprin register value determines the priority of the corresponding interrupt source. the lowest priority value is priority 0, and the highest priority value is priority 20. the index value of each interrupt source is written to one of the above 21 positions (see figure 13-4). the position value then becomes the written interrupt's priority value. the index value of each interrupt source is listed in table 13-1. table 13-5. interrupt priority register overview register offset address r/w description reset value intpri0 0x400c r/w interrupt priority register 0 0x03020100 intpri1 0x4010 r/w interrupt priority register 1 0x07060504 intpri2 0x4014 r/w interrupt priority register 2 0x0b0a0908 intpri3 0x4018 r/w interrupt priority register 3 0x0f0e0d0c intpri4 0x401c r/w interrupt priority register 4 0x13121110 intpri5 0x4020 r/w interrupt priority register 5 0x00000014 intpri0 30 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 19 20 21 22 23 24 25 26 27 28 29 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 priority3 priority7 priority11 priority15 priority19 priority2 priority6 priority10 priority14 priority18 priority1 priority5 priority9 priority13 priority17 priority0 priority4 priority8 priority12 priority16 priority20 intpri1 intpri2 intpri3 intpri4 intpri5 high priority low priority low priority high priority figure 13-4. interrupt priority register (intprin)
S3C4530A interrupt controller 13- 7 interrupt offset register the interrupt offset register, intoffset, contains the interrupt offset address of the interrupt, which has the highest priority among the pending interrupts. the content of the interrupt offset address is "bit position value of the interrupt source << 2". if all interrupt pending bits are "0" when you read this register, the return value is "0x00000054". this register is valid only under the irq or fiq mode in the arm7tdmi. in the interrupt service routine, you should read this register before changing the cpu mode. intoset_fiq/intoset_irq register can be used to get the highest priority interrupt without cpu mode change. other usages are similar to intoffset. note if the lowest interrupt priority (priority 0) is pending, the intoffset value will be "0x00000000". the reset value will, therefore, be changed to "0x00000054" (to be differentiated from interrupt pending priority 0). table 13-6. intoffset register register offset address r/w description reset value intoffset 0x4024 r interrupt offset register 0x00000054 intoset_fiq 0x4030 r fiq interrupt offset register 0x00000054 intoset_irq 0x4034 r irq interrupt offset register 0x00000054
interrupt controller S3C4530A 13- 8 interrupt pending by priority register the interrupt pending by priority register, intpndpri, contains interrupt pending bits, which are re-ordered by the intprin register settings. intpndpri[20] is mapped to the interrupt source of whichever bit index is written into the priority 20 field of the intprin registers. this register is useful for testing. to validate the interrupt pending by priority value, you can obtain the highest priority pending interrupt from the interrupt offset register, intoffset. table 13-7. intpndpri register register offset address r/w description reset value intpndpri 0x4028 r interrupt pending by priority 0x00000000 interrupt pending test register the interrupt pending test register, intpndtst, is used to set or clear intpnd and intpndpri. if user writes data to this register, it is written into both the intpnd register and intpndpri register. the interrupt pending test register, intpndtst, is also useful for testing. for intpnd, the same bit position is updated with the new coming data. for intpndpri, the mapping bit position by intprin registers is updated with the new coming data to keep with the contents of the intpnd register. table 13-8. intpndtst register register offset address r/w description reset value intpndtst 0x402c w interrupt pending test register 0x00000000
S3C4530A electrical data 14- 1 14 electrical data overview this chapter describes the S3C4530A electrical data. absolute maximum ratings table 14-1. absolute maximum ratings parameter symbol rating units supply voltage v dd /v dda ? 0.3 to 3.8 v dc input voltage v in 3.3 v i/o ? 0.3 to v dd + 0.3 v 5 v-tolerant ? 0.3 to 5.5 dc input current i in ### 10 ma operating temperature t opr 0 to 70 ### c storage temperature t stg ? 40 to 125 ### c absolute maximum ratings table 14-2. recommended operating conditions parameter symbol rating units supply voltage v dd /v dda 3.0 to 3.6 v oscillator frequency f osc 10 to 50 mhz external loop filter capacitance l f 820 pf commercial temperature t a 0 to 70 ### c note: it is strongly recommended that all the supply pins (v dd /v dda ) be powered from the same source to avoid power latch-up.
electrical data s3c 4530a 14- 2 d.c. electrical characteristics table 14-3. d.c electrical characteristics v dd =3.3v 0.3 v, v ext = 5 0.25 v, t a = 0 to 70 c (in case of 5 v-tolerant i/o) parameter symbol conditions min typ max unit high level input voltage lvcmos interface v ih (1) ? 2.0 ? ? v low level input voltage lvcmos interface v il (1) ? ? ? 0.8 v switching threshold vt lvcmos ? 1.4 ? v schmitt trigger positive-going threshold vt+ lvcmos ? ? 2.0 schmitt trigger negative-going threshold vt? lvcmos 0.8 ? ? high level input current input buffer i ih v in = v dd - 10 ? 10 m a input buffer with pull-up 10 30 60 low level input current input buffer i il v in = v ss - 10 ? 10 m a input buffer with pull- down - 60 - 30 - 10 high level output voltage type b1 to b16 (2) v oh i oh = ? 1 m a v dd - 0.05 ? ? v type b1 i oh = ? 1 ma 2.4 type b2 i oh = ? 2 ma type b4 i oh = ? 4 ma type b6 i oh = ? 6 ma low level output voltage type b1 to b16 (2) v ol i ol = 1 m a 0.05 v type b1 i ol = 1 ma 0.4 type b2 i ol = 2 ma type b4 i ol = 4 ma type b6 i ol = 6 ma tri-state output leakage current i oz v out = v ss or v dd - 10 10 m a maximum operating current i dd v dd = 3.6 v , f mclk = 50mhz 230 ma notes: 1. all 5 v-tolerant inputs have less than 0.2 v hysterics. 2. type b 1 means 1ma output driver cells, and type b6/b24 means 6ma/24ma output driver cells.
S3C4530A electrical data 14- 3 table 14-4. a.c electrical characteristics (t a = 0 to 70 c, v dd = 3.0v to 3.6 v) signal name description min max unit t mclkod mclko rising edge delay for internal negative edge clock -0.44 -0.3 n t emz memory control signal high-z time 19.55 19.55 p t emrs extmreq setup time 2.26 p t emrh extmreq hold time 0 p t emar extmack rising edge delay time 5.55 11.20 p t emaf extmack falling edge delay time 3.68 10.41 p t addrh address hold time 4.28 9.29 p t addrd address delay time 5.41 11.93 p t nrcs rom/sram/flash bank chip select delay time 4.71 10.31 p t nroe rom/sram or external i/o bank output enable delay 4.70 10.27 p t nwbe rom/sram or external i/o bank write byte enable delay 5.23 11.70 n t rdh read data hold time 10.85 p t wdd write data delay time (sram or external i/o) 0 p t wdh write data hold time (sram or external i/o) 2.29 5.27 n t nrasf dram ras signal active delay 2.15 4.32 p t nrasr dram ras signal release delay 4.11 8.32 n tncasf dram cas signal read active delay 4.95 10.88 p t ncasr dram cas signal release read delay time 3.93 8.56 n tncaswf dram cas signal write active delay 4.39 9.67 n t ncaswr dram cas signal release write delay time 4.23 9.17 p t ndwe dram bank write enable delay time 4.27 10.37 p t ndoe dram bank out enable delay time 7.10 16.28 p t necs external i/o bank chip select delay time 4.79 10.48 p t wddd dram write data delay time (dram) 17.63 17.17 p t wddh dram write data hold time (dram) 3.56 3.65 p t ws external wait setup time 11.96 p t wh external wait hold time 0 p note: the value (n) is calculated from mclko falling. the others are from mclko rising.
electrical data s3c 4530a 14- 4 notes
S3C4530A mechanical data 15- 1 1 5 mechanical data overview the S3C4530A is available in a 208-pin qfp package (208-qfp-2828).
mechanical data S3C4530A 15- 2 208-qfp-2828b #144 28.00 bsc 30.60 bsc 28.00 bsc 30.60 bsc 0.08 max 0.15 + 0.05 - 0.06 0-7 note : dimensions are in millimeters. #1 0.45-0.75 0.25 min 3.40 0.20 4.10 max 0.50 bsc (1.25) + 0.07 - 0.03 0.20 0.08 max figure 15-1. 208-qfp-2828b package dimensions

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